Conference Agenda

Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).

 
 
Session Overview
Date: Monday, 28/Oct/2024
1:00pm
-
5:00pm
Tutorial1: Mixed mode design using Open Source tools
Tutorial 2: Mixed-Precision Quantization: From DNN Training to Hardware Acceleration
Date: Tuesday, 29/Oct/2024
9:00am
-
9:20am
Opening
Location: Amfi (1st floor)
Chair: Jari Nurmi, Tampere University
Chair: Joachim Rodrigues, Lund University
9:20am
-
10:20am
Keynote: Stefan Wallentowitz
Location: Amfi (1st floor)
Chair: Joachim Rodrigues, Lund University
10:20am
-
11:00am
Plenary1
Location: Amfi (1st floor)
Chair: Joachim Rodrigues, Lund University
 
10:20am - 10:40am

An On-chip Digital Aging Sensor Circuit utilizing Leakage-current based Charge Accumulation

Kimiyoshi Usami, Mina Fukushima, Songxiang Wang, Kaito Nagai

Shibaura Institute of Technology, Japan



10:40am - 11:00am

Novel Circuit for In-Memory Computing within STT-RAM Memory Blocks

Pegah Shafaghi, Yasser Rezaeiyan, Sonal Shreya, Farshad Moradi, Hooman Farkhani

Aarhus University, Denmark

11:00am
-
11:40am
Posters Day1 and Coffee
 

Hardware-accelerated Compression Core on RISC-V for Online-BCG Data Reduction

Kazi Mohammad Abidur Rahman, Abdelrahman Noshy Abdelalim Ahmed, Goerschwin Fey, Ulf Kulau

Hamburg University of Technology, Germany



Implementation of the Tagged Geometric History Length Access Interval Predictor

Viktor Razilov1, Emil Matúš1, Gerhard Fettweis1,2

1: Technische Universität Dresden, Germany; 2: Barkhausen Institut, Dresden, Germany



On-chip READ and WRITE Circuits for Multi-bit Ferroelectric Tunnel Junction Memory

John Reuben1, Suzanne Lancaster2, Dietmar Fey1, Stefan Slesazeck2

1: Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany; 2: NaMLab gGmbH



A Clock Duty Cycle Correction Circuitry for Ultra-Wide Frequency Range using Nested Loops

Raghavendra Rukmani Gowrishankar, Kamlesh Satyadev Singh, Milind Gopal Agrawal

Advanced Micro Devices



Design of Single-Bit Switched-Capacitor $\Delta\Sigma$ Modulators Employing Fast-Settling Techniques

Alessandro Catania, Francesco Gagliardi, Michele Dei

Department of Information Engineering - University of Pisa, Italy



Tywaves: A Typed Waveform Viewer for Chisel

Raffaele Meloni1, H. Peter Hofstee1,2, Zaid Al-Ars1

1: Delft University of Technology, Delft, The Netherlands; 2: IBM Infrastructure, Austin, Texas, US



Cycle Count Estimation of VLIW Processors Using Machine Learning

Kari Hepola1, Jatan Shrestha2, Joonas Multanen1, Vivienne Wang2, Joni Pajarinen2, Pekka Jääskeläinen1,3

1: Tampere University, Finland; 2: Aalto University, Finland; 3: Intel Finland Oy



FPGA-Based Hardware Acceleration for Deep Learning in Mobile Robotics

Yasir Al-Ameri, Minh Nguyen, Tomi Westerlund

University of Turku, Finland

11:40am
-
12:40pm
Efficient FPGA & ASIC designs
Location: Danssalen (2nd floor)
Chair: Peeter Ellervee, Tallinn University of Technology
 
11:40am - 12:00pm

Fully Automated Implementation of Reservoir Computing Models on FPGAs for Nanosecond Inference Times

Fabian Legl1, Jonas Kantic2

1: IFTA Ingenieurbuero fuer Thermoakustik GmbH, Germany; 2: Technical University of Munich, TUM School of Computation, Information and Technology, Department of Computer Engineering, Germany



12:00pm - 12:20pm

Exploiting SORN-Arithmetic for Efficient Cross Correlation in Low-Complexity FPGAs

Jochen Rust1, Marvin Henkel1, Nils Hülsmeier2, Moritz Bärthel2, Steffen Paul2

1: HAW Hamburg, Germany; 2: University of Bremen, Germany



12:20pm - 12:40pm

VLSI integration of a RO-based PUF into a 65 nm technology.

Pau Ortega-Castro, Felipe Rojas-Muñoz, Jose M. Mora-Gutiérrez, Piedad Brox, Macarena C. Martínez-Rodríguez

Instituto de Microelectrónica de Sevilla (CSIC-US), Spain

RISC-V Security and Real-Time Operation
Location: Amfi (1st floor)
Chair: Luca Pezzarossa, Technical University of Denmark
 
11:40am - 12:00pm

A Systematic Comparison of Side-channel Countermeasures for RISC-V-based SoCs

Abolfazl Sajadi1, Nusa Zidaric1, Todor Stefanov1, Nele Mentens1,2

1: LIACS, Leiden University, Leiden, The Netherlands; 2: ES&S, COSIC, ESAT, KU Leuven, Leuven, Belgium



12:00pm - 12:20pm

Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case Study

Mohammad Reza Heidari Iman1, Sallar Ahmadi-Pour2, Rolf Drechsler2,3, Tara Ghasempouri1

1: Tallinn University of Technology; 2: University of Bremen; 3: Cyber-Physical Systems, DFKI GmbH



12:20pm - 12:40pm

Towards modularity of the Rust RTIC real-time scheduling framework

Zakaria Madaoui1, Henri Lunnikivi1, Pawel Dzialo1,2, Per Lindgren2,1

1: Tampere University, Finland; 2: Luleå University of Technology, Sweden

12:40pm
-
1:40pm
Lunch
1:40pm
-
2:40pm
Keynote: Farshad Moradi
Location: Amfi (1st floor)
Chair: Peeter Ellervee, Tallinn University of Technology
2:40pm
-
3:00pm
Plenary2
Location: Amfi (1st floor)
Chair: Peeter Ellervee, Tallinn University of Technology
 
2:40pm - 3:00pm

Trustworthy Silicon: An MPSoC for a Secure Operating System

Sebastian Haas, Christopher Dunkel, Friedrich Pauls, Mattis Hasler, Yogesh Verma

Barkhausen Institut, Germany

3:00pm
-
3:40pm
Posters Day1 and Coffee

The same posters as on morning coffee.

3:40pm
-
5:20pm
Transceiver Building Blocks
Location: Danssalen (2nd floor)
Chair: Ming Shen, Aalborg
 
3:40pm - 4:00pm

On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers

Edoardo Baiesi Fietta1, David Seebacher2, Davide Ponton2, Andrea Bevilacqua1

1: University of Padua, Italy; 2: Infineon Technologies Austria, Austria



4:00pm - 4:20pm

MMIC Design for Radiometer Receiver at 240 GHz in 0.13 μm SiGe BiCMOS Technology

Md Najmussadat1, Yehia Tawfik1, Raju Ahamed1, Mikko Varonen2, Dristy Parveg2, Antti Lamminen2, Pekka Pursula2, Kari Halonen1

1: Aalto University, Finland; 2: VTT Technical Research Centre of Finland



4:20pm - 4:40pm

A 0.00027mm2 1.2V 0.089pJ/bit 10Gbps 41.6GHz Standard-Cell-Based Passive-Less Wireless OOK Transmitter with On-Chip Antenna in 12nm FinFET

Hiroaki Kitaike1, Hironori Tagawa1, Masaya Kaneko2, Jin Nakamura2, Shufan Xu1, Ruilin Zhang1, Kunyang Liu1, Hiroki Wakatsuchi3, Kyoya Takano4, Hirofumi Shinohara1, Kiichi Niitsu1

1: Kyoto University, Japan; 2: Meitec Corp., Kyoto, Japan; 3: Nagoya Institute of Technology, Nagoya, Japan; 4: Tokyo University of Science, Tokyo, Japan



4:40pm - 5:00pm

Enhanced Mixer-First Receiver Using Series Switch N-Path Passive Mixer for Millimeter-Wave 5G Applications

Fatemeh Abbassi1,2, Timm Ostermann2, Christoph Wagner1

1: Silicon Austria Labs, Austria; 2: Johannes Kepler Universität Linz: JKU, Austria



5:00pm - 5:20pm

A 2Hz 1.2-2V 0.22-9nW 0.007mm2 65nm CMOS Down-Converter-Less Multiple-Output Clock Generator Using Stacked a Ring Oscillator and Frequency Dividers for Scaling-Friendly IoTs

You Wu1, Kei Awano1, Kento Okamura1, Teruaki Ono1, Kohei Sakamoto1, Hiroaki Kitaike1, Hironori Tagawa1, Jin Nakamura2, Masaya Kaneko2, Yuta Kimura3, Hiroaki Nakamura3, Shufan Xu1, Ruilin Zhang1, Kunyang Liu1, Hirofumi Shinohara1, Kiichi Niitsu1

1: Kyoto University, Japan; 2: Meitec Corporation, Kyoto, Japan; 3: Shuhari System, Fukuoka, Japan

Special Session: RISC-V
Location: Amfi (1st floor)
Chair: Mattis Hasler, Barkhauseninstitut gGmbH
 
3:40pm - 4:00pm

AMPER-X: Adaptive Mixed-Precision RISC-V Core for Embedded Applications

Ahmad Othman, Ahmed Kamaleldin, Diana Göhringer

TU Dresden, Germany



4:00pm - 4:20pm

Automated Intrinsic Support for ISA Extensions: Enhancing Software Generation for RISC-V and Beyond

Mayuri Bhadra1,2, Stephanie Ecker1,3, Daniel Albert1, Ravindra Ramaiah1, Sebastian Prebeck1, Wolfgang Ecker1,2

1: Infineon Technologies AG, Germany; 2: Technical University of Munich, Munich, Germany; 3: Chipglobe GmbH, Neubiberg, Germany



4:20pm - 4:40pm

Fully Automatic Compiler Retargeting and CVX-IF Hardware Interface Generation for RISC-V Custom Instructions

Kari Hepola1, Tharaka Ranasinghe Arachchige1, Joonas Multanen1, Pekka Jääskeläinen1,2

1: Tampere University, Finland; 2: Intel Finland Oy



4:40pm - 5:00pm

Hardware Solutions for Eliminating Context Switching Latency in Processor-Based Hard Real-Time Systems

Antti Nurmi, Abdesattar Kalache, Timo D. Hämäläinen

Tampere University, Finland



5:00pm - 5:20pm

RISC-V Triplet: Tapeouts for Security Applications

Jonas Schupp1, Patrick Karl1, Jens Nöpel1, Alexander Hepp1, Tim Music1, Georg Sigl1,2

1: Technical University of Munich, Munich, Germany; 2: Fraunhofer Institute for Applied and Integrated Security (AISEC), Garching, Germany

7:00pm
-
10:00pm
Dinner
Location: Grand Hotel
Date: Wednesday, 30/Oct/2024
9:00am
-
10:00am
Keynote: Timo D. Hämäläinen
Location: Amfi (1st floor)
Chair: Jari Nurmi, Tampere University
10:00am
-
11:00am
Optimization and tools for HW-implemented AI
Location: Amfi (1st floor)
Chair: Joachim Rodrigues, Lund University
 
10:00am - 10:20am

Towards a General Compilation Approach for On-device Training in Embedded Systems

Iuliia Topko, Tanja Harbaum, Juergen Becker

Karlsruhe Institute of Technology, Germany



10:20am - 10:40am

Adaptive Quantization of Graph Convolutional Networks with Hardware-Aware On-device Training

Jose Nunez-Yanez

Linkoping University, Sweden



10:40am - 11:00am

Leveraging Dynamic Range Analysis for Efficient Post-Training Quantization in Graph Convolutional Networks

Hadi Mousanejad Jeddi, Mahdieh Grailoo, Jose Nunez-Yanez

Linköping University, Sweden

SoC and NoC Architecture
Location: Danssalen (2nd floor)
Chair: Jari Nurmi, Tampere University
 
10:00am - 10:20am

QoS-Aware Dynamic Voltage-Frequency Scaling for Mixed-Critical Systems based on Shielded Reinforcement Learning

Florian Maurer, Michael Meidinger, Yiming Lu, Thomas Hallermeier, Anmol Surhonne, Thomas Wild, Andreas Herkersdorf

Technical University of Munich, Germany



10:20am - 10:40am

Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis

Sergei Devadze1, Christine Elizabeth Nielsen2, Dmitri Mihhailov1, Peeter Ellervee1

1: Tallinn University of Technology, Estonia; 2: National Institute of Chemical Physics and Biophysics, Estonia



10:40am - 11:00am

Improving Reliability in Network-on-Chip with Trust-based Adaptive Routing Approaches

Sebastian Jaster1, Julian Haase2, Diana Göhringer2,3, Elke Franz1

1: Chair of Privacy and Security, Technische Universität Dresden, Germany; 2: Chair of Adaptive Dynamic Systems, Technische Universität Dresden, Germany; 3: Centre for Tactile Internet with Human-in-the-Loop (CeTI), Technische Universität Dresden, Germany

11:00am
-
11:40am
Posters Day2 and Coffee
 

Design Space Exploration of Dynamically Reconfigurable Network-on-Chip Architectures with Multiobjective Evolutionary Algorithms

Julian Haase, Najdet Charaf, Alexander Groß, Diana Göhringer

Technische Universität Dresden, Germany



RV-ProViler: Evaluating RISC-V ISA for Application-Specific Requirements

Muhammad Ali, Ensieh Aliagha, Mahmoud Elnashar, Diana Göhringer

Technische Universität Dresden, Germany



Design of a Karatsuba Multiplier to Accelerate Digital Signature Schemes on Embedded Systems

Pablo Navarro-Torrero, Eros Camacho-Ruiz, Macarena C. Martínez-Rodríguez, Piedad Brox

Instituto de Microelectrónica de Sevilla (IMSE-CNM), CSIC-US, Seville, Spain



High linear on-chip delay generator for a depth profiling CMOS SPAD Raman sensor

Belal Amin, Ilkka Nissinen

University of Oulu, Finland



A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces

Mohammadreza Esmaeilpour, Jan Lappas, Christian Weis, Norbert Wehn

University of Kaiserslautern-Landau (RPTU), Germany



Compact and Efficient Switching Power Amplifier for Micro-NMR Applications

Mohammed Al Shihabi, Natachai Terawatsakul, Alireza Saberkari

Linköping University, Sweden



Joint CPU-FPGA Hardware-Aware Quantized Training of Graph Convolutional Networks

Olle Hansson, Oscar Gustafsson, Jose Nunez-Yanez

Linköping University, Sweden



FPGA-based Resource Efficient High Throughput Object Detection Using Pipelined CNN and Custom SSD

Rashed Al Amin, Roman Obermaisser

Institute for Embedded Systems, University of Siegen, 57076 Siegen, Germany



Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-Correction

Oliver Schrape1, Anselm Breitenreiter1, Li Lu1, Marko Andjelkovic1, Ernesto Pun-Garcia3,4, Marisa Lopez-Vallejo4, Milos Krstic1,2

1: IHP GmbH, Germany; 2: University of Potsdam, Germany; 3: Arquimea Research Center, Spain; 4: IPTC, ETSI Telecomunicacion, Universidad Politecnica de Madrid, Spain



Quantitative Evaluation on the Limits of SORN Arithmetic Hardware Circuits

Moritz Bärthel1, Nils Hülsmeier1, Jochen Rust2, Steffen Paul1

1: ITEM.me, University of Bremen, Bremen, Germany; 2: Hamburg University of Applied Sciences, Hamburg, Germany

11:40am
-
12:40pm
Energy Harvesting Circuits
Location: Danssalen (2nd floor)
Chair: Victor Åberg, Lund University
 
11:40am - 12:00pm

Analysis and Design of a Reconfigurable RF-DC Rectifier for RF Energy Harvesting Systems

André Ponchet1,3, Javad Bagheri Asli1, Alireza Saberkari1, César Casañas1, Atila Alvandpour1, Ingemar Söderquist2, Osamu Saotome3

1: Linkoping University, Sweden; 2: SAAB Group; 3: Aeronautics Institute of Technology - ITA



12:00pm - 12:20pm

On the Optimal Design of Integrated AC-DC Converters for Energy Harvesting

Luca Bellemo, Giorgio Spiazzi, Andrea Bevilacqua

DEI, University of Padova, Italy



12:20pm - 12:40pm

High-Sensitivity Hybrid Compensated RF-to-DC Converter for Low-Power RFEH Applications

Wei Cao, Alireza Saberkari, Atila Alvandpour

Linkoping University, Sweden

Hardware accelerated AI applications
Location: Amfi (1st floor)
Chair: Atila Alvandpour, Linköping University
 
11:40am - 12:00pm

Hardware Acceleration of Molecular Property Graph Prediction on a Heterogeneous Edge Platform

Mahdieh Grailoo1, Tooraj Nakoubin2, Jose Nunez-Yanez1

1: Linköping University, Sweden; 2: University of Texas at Dallas



12:00pm - 12:20pm

Inter-node Communication in Multi-FPGA-based Computational Neuroscience Simulators: PHY-to-Link

Vida Sobhani, Jan Lorenz, Tobias Gemmeke

Chair of Integrated Digital Systems and Circuit Design (IDS), RWTH University, Germany



12:20pm - 12:40pm

In-door Positioning using Distributed Massive MIMO: Architecture and FPGA Implementation

Dumitra Iancu, Lina Tinnerberg, Ove Edfors, Liang Liu

Lund University, Sweden

12:40pm
-
1:40pm
Lunch
1:40pm
-
2:40pm
Keynote: Ted Johansson
Location: Amfi (1st floor)
Chair: Jussi Ryynänen, Aalto University
2:40pm
-
3:00pm
Plenary3
Location: Amfi (1st floor)
Chair: Jari Nurmi, Tampere University
 
2:40pm - 3:00pm

Multi-Stream FFT Architectures for a Distributed MIMO Large Intelligent Surfaces Testbed

Mikael Henriksson, Hugo Winbladh, Oscar Gustafsson

Linköping University, Sweden

3:00pm
-
3:40pm
Posters Day2 and Coffee

The same posters as on morning coffee.

3:40pm
-
4:20pm
Plenary4
Location: Amfi (1st floor)
Chair: Jari Nurmi, Tampere University
Chair: Dag T. Wisland, UiO
 
3:40pm - 4:00pm

A 505 nW Programmable NanoController in 22 nm FDSOI-CMOS for Autonomous Ultra-Low-Power Mixed-Signal SoCs

Moritz Weißbrich1, Alexander Meyer2, Adilet Dossanov2, Vadim Issakov2, Guillermo Payá-Vayá1

1: Chair for Chip Design for Embedded Computing, TU Braunschweig, Germany; 2: Institute for CMOS Design, TU Braunschweig, Germany



4:00pm - 4:20pm

ZuSE-KI-Mobil AI Chip Design Platform: An Overview

Shaown Mojumder1, Simon Friedrich1, Emil Matúš1, Gerhard Fettweis1, Matthias Lueders2, Martin Friedrich2, Oliver Renke2, Holger Blume2, Julian Hoefer3, Patrick Schmidt3, Juergen Becker3, Darius Grantz4, Markus Kock4, Jens Benndorf4, Nael Fasfous5, Pierpaolo Mori5, Hans-Joerg Voegel5, Samira Ahmadifarsani6, Leonidas Kontopoulos6, Ulf Schlichtmann6, Kay Bierzynski7

1: Technical University of Dresden; 2: Leibniz University Hannover; 3: Karlsruhe Institute of Technology; 4: Dream Chip Technologies GmbH; 5: Bayerische Motoren Werke Aktiengesellschaft (BMW AG); 6: Technical University of Munich; 7: Infineon Technologies AG Munich

4:20pm
-
4:40pm
Awards and Closing
Location: Amfi (1st floor)
Chair: Jari Nurmi, Tampere University

 
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