An On-chip Digital Aging Sensor Circuit utilizing Leakage-current based Charge Accumulation

Kimiyoshi Usami, Mina Fukushima, Songxiang Wang, Kaito Nagai

Shibaura Institute of Technology, Japan

Novel Circuit for In-Memory Computing within STT-RAM Memory Blocks

Pegah Shafaghi, Yasser Rezaeiyan, Sonal Shreya, Farshad Moradi, Hooman Farkhani

Aarhus University, Denmark

Hardware-accelerated Compression Core on RISC-V for Online-BCG Data Reduction

Kazi Mohammad Abidur Rahman, Abdelrahman Noshy Abdelalim Ahmed, Goerschwin Fey, Ulf Kulau

Hamburg University of Technology, Germany

Implementation of the Tagged Geometric History Length Access Interval Predictor

Viktor Razilov¹, Emil Matúš¹, Gerhard Fettweis^1,2

1: Technische Universität Dresden, Germany; 2: Barkhausen Institut, Dresden, Germany

On-chip READ and WRITE Circuits for Multi-bit Ferroelectric Tunnel Junction Memory

John Reuben¹, Suzanne Lancaster², Dietmar Fey¹, Stefan Slesazeck²

1: Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany; 2: NaMLab gGmbH

A Clock Duty Cycle Correction Circuitry for Ultra-Wide Frequency Range using Nested Loops

Raghavendra Rukmani Gowrishankar, Kamlesh Satyadev Singh, Milind Gopal Agrawal

Advanced Micro Devices

Design of Single-Bit Switched-Capacitor $\Delta\Sigma$ Modulators Employing Fast-Settling Techniques

Alessandro Catania, Francesco Gagliardi, Michele Dei

Department of Information Engineering - University of Pisa, Italy

Tywaves: A Typed Waveform Viewer for Chisel

Raffaele Meloni¹, H. Peter Hofstee^1,2, Zaid Al-Ars¹

1: Delft University of Technology, Delft, The Netherlands; 2: IBM Infrastructure, Austin, Texas, US

Cycle Count Estimation of VLIW Processors Using Machine Learning

Kari Hepola¹, Jatan Shrestha², Joonas Multanen¹, Vivienne Wang², Joni Pajarinen², Pekka Jääskeläinen^1,3

1: Tampere University, Finland; 2: Aalto University, Finland; 3: Intel Finland Oy

FPGA-Based Hardware Acceleration for Deep Learning in Mobile Robotics

Yasir Al-Ameri, Minh Nguyen, Tomi Westerlund

University of Turku, Finland

Fully Automated Implementation of Reservoir Computing Models on FPGAs for Nanosecond Inference Times

Fabian Legl¹, Jonas Kantic²

1: IFTA Ingenieurbuero fuer Thermoakustik GmbH, Germany; 2: Technical University of Munich, TUM School of Computation, Information and Technology, Department of Computer Engineering, Germany

Exploiting SORN-Arithmetic for Efficient Cross Correlation in Low-Complexity FPGAs

Jochen Rust¹, Marvin Henkel¹, Nils Hülsmeier², Moritz Bärthel², Steffen Paul²

1: HAW Hamburg, Germany; 2: University of Bremen, Germany

VLSI integration of a RO-based PUF into a 65 nm technology.

Pau Ortega-Castro, Felipe Rojas-Muñoz, Jose M. Mora-Gutiérrez, Piedad Brox, Macarena C. Martínez-Rodríguez

Instituto de Microelectrónica de Sevilla (CSIC-US), Spain

A Systematic Comparison of Side-channel Countermeasures for RISC-V-based SoCs

Abolfazl Sajadi¹, Nusa Zidaric¹, Todor Stefanov¹, Nele Mentens^1,2

1: LIACS, Leiden University, Leiden, The Netherlands; 2: ES&S, COSIC, ESAT, KU Leuven, Leuven, Belgium

Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case Study

Mohammad Reza Heidari Iman¹, Sallar Ahmadi-Pour², Rolf Drechsler^2,3, Tara Ghasempouri¹

1: Tallinn University of Technology; 2: University of Bremen; 3: Cyber-Physical Systems, DFKI GmbH

Towards modularity of the Rust RTIC real-time scheduling framework

Zakaria Madaoui¹, Henri Lunnikivi¹, Pawel Dzialo^1,2, Per Lindgren^2,1

1: Tampere University, Finland; 2: Luleå University of Technology, Sweden

Trustworthy Silicon: An MPSoC for a Secure Operating System

Sebastian Haas, Christopher Dunkel, Friedrich Pauls, Mattis Hasler, Yogesh Verma

Barkhausen Institut, Germany

On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers

Edoardo Baiesi Fietta¹, David Seebacher², Davide Ponton², Andrea Bevilacqua¹

1: University of Padua, Italy; 2: Infineon Technologies Austria, Austria

MMIC Design for Radiometer Receiver at 240 GHz in 0.13 μm SiGe BiCMOS Technology

Md Najmussadat¹, Yehia Tawfik¹, Raju Ahamed¹, Mikko Varonen², Dristy Parveg², Antti Lamminen², Pekka Pursula², Kari Halonen¹

1: Aalto University, Finland; 2: VTT Technical Research Centre of Finland

A 0.00027mm2 1.2V 0.089pJ/bit 10Gbps 41.6GHz Standard-Cell-Based Passive-Less Wireless OOK Transmitter with On-Chip Antenna in 12nm FinFET

Hiroaki Kitaike¹, Hironori Tagawa¹, Masaya Kaneko², Jin Nakamura², Shufan Xu¹, Ruilin Zhang¹, Kunyang Liu¹, Hiroki Wakatsuchi³, Kyoya Takano⁴, Hirofumi Shinohara¹, Kiichi Niitsu¹

1: Kyoto University, Japan; 2: Meitec Corp., Kyoto, Japan; 3: Nagoya Institute of Technology, Nagoya, Japan; 4: Tokyo University of Science, Tokyo, Japan

Enhanced Mixer-First Receiver Using Series Switch N-Path Passive Mixer for Millimeter-Wave 5G Applications

Fatemeh Abbassi^1,2, Timm Ostermann², Christoph Wagner¹

1: Silicon Austria Labs, Austria; 2: Johannes Kepler Universität Linz: JKU, Austria

A 2Hz 1.2-2V 0.22-9nW 0.007mm2 65nm CMOS Down-Converter-Less Multiple-Output Clock Generator Using Stacked a Ring Oscillator and Frequency Dividers for Scaling-Friendly IoTs

You Wu¹, Kei Awano¹, Kento Okamura¹, Teruaki Ono¹, Kohei Sakamoto¹, Hiroaki Kitaike¹, Hironori Tagawa¹, Jin Nakamura², Masaya Kaneko², Yuta Kimura³, Hiroaki Nakamura³, Shufan Xu¹, Ruilin Zhang¹, Kunyang Liu¹, Hirofumi Shinohara¹, Kiichi Niitsu¹

1: Kyoto University, Japan; 2: Meitec Corporation, Kyoto, Japan; 3: Shuhari System, Fukuoka, Japan

AMPER-X: Adaptive Mixed-Precision RISC-V Core for Embedded Applications

Ahmad Othman, Ahmed Kamaleldin, Diana Göhringer

TU Dresden, Germany

Automated Intrinsic Support for ISA Extensions: Enhancing Software Generation for RISC-V and Beyond

Mayuri Bhadra^1,2, Stephanie Ecker^1,3, Daniel Albert¹, Ravindra Ramaiah¹, Sebastian Prebeck¹, Wolfgang Ecker^1,2

1: Infineon Technologies AG, Germany; 2: Technical University of Munich, Munich, Germany; 3: Chipglobe GmbH, Neubiberg, Germany

Fully Automatic Compiler Retargeting and CVX-IF Hardware Interface Generation for RISC-V Custom Instructions

Kari Hepola¹, Tharaka Ranasinghe Arachchige¹, Joonas Multanen¹, Pekka Jääskeläinen^1,2

1: Tampere University, Finland; 2: Intel Finland Oy

Hardware Solutions for Eliminating Context Switching Latency in Processor-Based Hard Real-Time Systems

Antti Nurmi, Abdesattar Kalache, Timo D. Hämäläinen

Tampere University, Finland

RISC-V Triplet: Tapeouts for Security Applications

Jonas Schupp¹, Patrick Karl¹, Jens Nöpel¹, Alexander Hepp¹, Tim Music¹, Georg Sigl^1,2

1: Technical University of Munich, Munich, Germany; 2: Fraunhofer Institute for Applied and Integrated Security (AISEC), Garching, Germany

Towards a General Compilation Approach for On-device Training in Embedded Systems

Iuliia Topko, Tanja Harbaum, Juergen Becker

Karlsruhe Institute of Technology, Germany

Adaptive Quantization of Graph Convolutional Networks with Hardware-Aware On-device Training

Jose Nunez-Yanez

Linkoping University, Sweden

Leveraging Dynamic Range Analysis for Efficient Post-Training Quantization in Graph Convolutional Networks

Hadi Mousanejad Jeddi, Mahdieh Grailoo, Jose Nunez-Yanez

Linköping University, Sweden

QoS-Aware Dynamic Voltage-Frequency Scaling for Mixed-Critical Systems based on Shielded Reinforcement Learning

Florian Maurer, Michael Meidinger, Yiming Lu, Thomas Hallermeier, Anmol Surhonne, Thomas Wild, Andreas Herkersdorf

Technical University of Munich, Germany

Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis

Sergei Devadze¹, Christine Elizabeth Nielsen², Dmitri Mihhailov¹, Peeter Ellervee¹

1: Tallinn University of Technology, Estonia; 2: National Institute of Chemical Physics and Biophysics, Estonia

Improving Reliability in Network-on-Chip with Trust-based Adaptive Routing Approaches

Sebastian Jaster¹, Julian Haase², Diana Göhringer^2,3, Elke Franz¹

1: Chair of Privacy and Security, Technische Universität Dresden, Germany; 2: Chair of Adaptive Dynamic Systems, Technische Universität Dresden, Germany; 3: Centre for Tactile Internet with Human-in-the-Loop (CeTI), Technische Universität Dresden, Germany

Design Space Exploration of Dynamically Reconfigurable Network-on-Chip Architectures with Multiobjective Evolutionary Algorithms

Julian Haase, Najdet Charaf, Alexander Groß, Diana Göhringer

Technische Universität Dresden, Germany

RV-ProViler: Evaluating RISC-V ISA for Application-Specific Requirements

Muhammad Ali, Ensieh Aliagha, Mahmoud Elnashar, Diana Göhringer

Technische Universität Dresden, Germany

Design of a Karatsuba Multiplier to Accelerate Digital Signature Schemes on Embedded Systems

Pablo Navarro-Torrero, Eros Camacho-Ruiz, Macarena C. Martínez-Rodríguez, Piedad Brox

Instituto de Microelectrónica de Sevilla (IMSE-CNM), CSIC-US, Seville, Spain

High linear on-chip delay generator for a depth profiling CMOS SPAD Raman sensor

Belal Amin, Ilkka Nissinen

University of Oulu, Finland

A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces

Mohammadreza Esmaeilpour, Jan Lappas, Christian Weis, Norbert Wehn

University of Kaiserslautern-Landau (RPTU), Germany

Compact and Efficient Switching Power Amplifier for Micro-NMR Applications

Mohammed Al Shihabi, Natachai Terawatsakul, Alireza Saberkari

Linköping University, Sweden

Joint CPU-FPGA Hardware-Aware Quantized Training of Graph Convolutional Networks

Olle Hansson, Oscar Gustafsson, Jose Nunez-Yanez

Linköping University, Sweden

FPGA-based Resource Efficient High Throughput Object Detection Using Pipelined CNN and Custom SSD

Rashed Al Amin, Roman Obermaisser

Institute for Embedded Systems, University of Siegen, 57076 Siegen, Germany

Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-Correction

Oliver Schrape¹, Anselm Breitenreiter¹, Li Lu¹, Marko Andjelkovic¹, Ernesto Pun-Garcia^3,4, Marisa Lopez-Vallejo⁴, Milos Krstic^1,2

1: IHP GmbH, Germany; 2: University of Potsdam, Germany; 3: Arquimea Research Center, Spain; 4: IPTC, ETSI Telecomunicacion, Universidad Politecnica de Madrid, Spain

Quantitative Evaluation on the Limits of SORN Arithmetic Hardware Circuits

Moritz Bärthel¹, Nils Hülsmeier¹, Jochen Rust², Steffen Paul¹

1: ITEM.me, University of Bremen, Bremen, Germany; 2: Hamburg University of Applied Sciences, Hamburg, Germany

Analysis and Design of a Reconfigurable RF-DC Rectifier for RF Energy Harvesting Systems

André Ponchet^1,3, Javad Bagheri Asli¹, Alireza Saberkari¹, César Casañas¹, Atila Alvandpour¹, Ingemar Söderquist², Osamu Saotome³

1: Linkoping University, Sweden; 2: SAAB Group; 3: Aeronautics Institute of Technology - ITA

On the Optimal Design of Integrated AC-DC Converters for Energy Harvesting

Luca Bellemo, Giorgio Spiazzi, Andrea Bevilacqua

DEI, University of Padova, Italy

High-Sensitivity Hybrid Compensated RF-to-DC Converter for Low-Power RFEH Applications

Wei Cao, Alireza Saberkari, Atila Alvandpour

Linkoping University, Sweden

Hardware Acceleration of Molecular Property Graph Prediction on a Heterogeneous Edge Platform

Mahdieh Grailoo¹, Tooraj Nakoubin², Jose Nunez-Yanez¹

1: Linköping University, Sweden; 2: University of Texas at Dallas

Inter-node Communication in Multi-FPGA-based Computational Neuroscience Simulators: PHY-to-Link

Vida Sobhani, Jan Lorenz, Tobias Gemmeke

Chair of Integrated Digital Systems and Circuit Design (IDS), RWTH University, Germany

In-door Positioning using Distributed Massive MIMO: Architecture and FPGA Implementation

Dumitra Iancu, Lina Tinnerberg, Ove Edfors, Liang Liu

Lund University, Sweden

Multi-Stream FFT Architectures for a Distributed MIMO Large Intelligent Surfaces Testbed

Mikael Henriksson, Hugo Winbladh, Oscar Gustafsson

Linköping University, Sweden

A 505 nW Programmable NanoController in 22 nm FDSOI-CMOS for Autonomous Ultra-Low-Power Mixed-Signal SoCs

Moritz Weißbrich¹, Alexander Meyer², Adilet Dossanov², Vadim Issakov², Guillermo Payá-Vayá¹

1: Chair for Chip Design for Embedded Computing, TU Braunschweig, Germany; 2: Institute for CMOS Design, TU Braunschweig, Germany

ZuSE-KI-Mobil AI Chip Design Platform: An Overview

Shaown Mojumder¹, Simon Friedrich¹, Emil Matúš¹, Gerhard Fettweis¹, Matthias Lueders², Martin Friedrich², Oliver Renke², Holger Blume², Julian Hoefer³, Patrick Schmidt³, Juergen Becker³, Darius Grantz⁴, Markus Kock⁴, Jens Benndorf⁴, Nael Fasfous⁵, Pierpaolo Mori⁵, Hans-Joerg Voegel⁵, Samira Ahmadifarsani⁶, Leonidas Kontopoulos⁶, Ulf Schlichtmann⁶, Kay Bierzynski⁷

1: Technical University of Dresden; 2: Leibniz University Hannover; 3: Karlsruhe Institute of Technology; 4: Dream Chip Technologies GmbH; 5: Bayerische Motoren Werke Aktiengesellschaft (BMW AG); 6: Technical University of Munich; 7: Infineon Technologies AG Munich