NorCAS 2024
IEEE Nordic Circuits and Systems Conference
October 29 - 30, 2024 | Lund, Sweden
Conference Agenda
Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).
|
Session Overview |
Date: Monday, 28/Oct/2024 | ||
1:00pm - 5:00pm |
Tutorial1: Mixed mode design using Open Source tools |
Tutorial 2: Mixed-Precision Quantization: From DNN Training to Hardware Acceleration |
Date: Tuesday, 29/Oct/2024 | ||
9:00am - 9:20am |
Opening Location: Amfi (1st floor) Chair: Jari Nurmi, Tampere University Chair: Joachim Rodrigues, Lund University |
|
9:20am - 10:20am |
Keynote: Stefan Wallentowitz Location: Amfi (1st floor) Chair: Joachim Rodrigues, Lund University |
|
10:20am - 11:00am |
Plenary1 Location: Amfi (1st floor) Chair: Joachim Rodrigues, Lund University An On-chip Digital Aging Sensor Circuit utilizing Leakage-current based Charge Accumulation Shibaura Institute of Technology, Japan 10:40am - 11:00am Novel Circuit for In-Memory Computing within STT-RAM Memory Blocks Aarhus University, Denmark |
|
11:00am - 11:40am |
Posters Day1 and Coffee Hardware-accelerated Compression Core on RISC-V for Online-BCG Data Reduction Hamburg University of Technology, Germany Implementation of the Tagged Geometric History Length Access Interval Predictor 1: Technische Universität Dresden, Germany; 2: Barkhausen Institut, Dresden, Germany On-chip READ and WRITE Circuits for Multi-bit Ferroelectric Tunnel Junction Memory 1: Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany; 2: NaMLab gGmbH A Clock Duty Cycle Correction Circuitry for Ultra-Wide Frequency Range using Nested Loops Advanced Micro Devices Design of Single-Bit Switched-Capacitor $\Delta\Sigma$ Modulators Employing Fast-Settling Techniques Department of Information Engineering - University of Pisa, Italy Tywaves: A Typed Waveform Viewer for Chisel 1: Delft University of Technology, Delft, The Netherlands; 2: IBM Infrastructure, Austin, Texas, US Cycle Count Estimation of VLIW Processors Using Machine Learning 1: Tampere University, Finland; 2: Aalto University, Finland; 3: Intel Finland Oy FPGA-Based Hardware Acceleration for Deep Learning in Mobile Robotics University of Turku, Finland |
|
11:40am - 12:40pm |
Efficient FPGA & ASIC designs Location: Danssalen (2nd floor) Chair: Peeter Ellervee, Tallinn University of Technology Fully Automated Implementation of Reservoir Computing Models on FPGAs for Nanosecond Inference Times 1: IFTA Ingenieurbuero fuer Thermoakustik GmbH, Germany; 2: Technical University of Munich, TUM School of Computation, Information and Technology, Department of Computer Engineering, Germany 12:00pm - 12:20pm Exploiting SORN-Arithmetic for Efficient Cross Correlation in Low-Complexity FPGAs 1: HAW Hamburg, Germany; 2: University of Bremen, Germany 12:20pm - 12:40pm VLSI integration of a RO-based PUF into a 65 nm technology. Instituto de Microelectrónica de Sevilla (CSIC-US), Spain |
RISC-V Security and Real-Time Operation Location: Amfi (1st floor) Chair: Luca Pezzarossa, Technical University of Denmark A Systematic Comparison of Side-channel Countermeasures for RISC-V-based SoCs 1: LIACS, Leiden University, Leiden, The Netherlands; 2: ES&S, COSIC, ESAT, KU Leuven, Leuven, Belgium 12:00pm - 12:20pm Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case Study 1: Tallinn University of Technology; 2: University of Bremen; 3: Cyber-Physical Systems, DFKI GmbH 12:20pm - 12:40pm Towards modularity of the Rust RTIC real-time scheduling framework 1: Tampere University, Finland; 2: Luleå University of Technology, Sweden |
12:40pm - 1:40pm |
Lunch |
|
1:40pm - 2:40pm |
Keynote: Farshad Moradi Location: Amfi (1st floor) Chair: Peeter Ellervee, Tallinn University of Technology |
|
2:40pm - 3:00pm |
Plenary2 Location: Amfi (1st floor) Chair: Peeter Ellervee, Tallinn University of Technology Trustworthy Silicon: An MPSoC for a Secure Operating System Barkhausen Institut, Germany |
|
3:00pm - 3:40pm |
Posters Day1 and Coffee The same posters as on morning coffee. |
|
3:40pm - 5:20pm |
Transceiver Building Blocks Location: Danssalen (2nd floor) Chair: Ming Shen, Aalborg On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers 1: University of Padua, Italy; 2: Infineon Technologies Austria, Austria 4:00pm - 4:20pm MMIC Design for Radiometer Receiver at 240 GHz in 0.13 μm SiGe BiCMOS Technology 1: Aalto University, Finland; 2: VTT Technical Research Centre of Finland 4:20pm - 4:40pm A 0.00027mm2 1.2V 0.089pJ/bit 10Gbps 41.6GHz Standard-Cell-Based Passive-Less Wireless OOK Transmitter with On-Chip Antenna in 12nm FinFET 1: Kyoto University, Japan; 2: Meitec Corp., Kyoto, Japan; 3: Nagoya Institute of Technology, Nagoya, Japan; 4: Tokyo University of Science, Tokyo, Japan 4:40pm - 5:00pm Enhanced Mixer-First Receiver Using Series Switch N-Path Passive Mixer for Millimeter-Wave 5G Applications 1: Silicon Austria Labs, Austria; 2: Johannes Kepler Universität Linz: JKU, Austria 5:00pm - 5:20pm A 2Hz 1.2-2V 0.22-9nW 0.007mm2 65nm CMOS Down-Converter-Less Multiple-Output Clock Generator Using Stacked a Ring Oscillator and Frequency Dividers for Scaling-Friendly IoTs 1: Kyoto University, Japan; 2: Meitec Corporation, Kyoto, Japan; 3: Shuhari System, Fukuoka, Japan |
Special Session: RISC-V Location: Amfi (1st floor) Chair: Mattis Hasler, Barkhauseninstitut gGmbH AMPER-X: Adaptive Mixed-Precision RISC-V Core for Embedded Applications TU Dresden, Germany 4:00pm - 4:20pm Automated Intrinsic Support for ISA Extensions: Enhancing Software Generation for RISC-V and Beyond 1: Infineon Technologies AG, Germany; 2: Technical University of Munich, Munich, Germany; 3: Chipglobe GmbH, Neubiberg, Germany 4:20pm - 4:40pm Fully Automatic Compiler Retargeting and CVX-IF Hardware Interface Generation for RISC-V Custom Instructions 1: Tampere University, Finland; 2: Intel Finland Oy 4:40pm - 5:00pm Hardware Solutions for Eliminating Context Switching Latency in Processor-Based Hard Real-Time Systems Tampere University, Finland 5:00pm - 5:20pm RISC-V Triplet: Tapeouts for Security Applications 1: Technical University of Munich, Munich, Germany; 2: Fraunhofer Institute for Applied and Integrated Security (AISEC), Garching, Germany |
7:00pm - 10:00pm |
Dinner Location: Grand Hotel |
Date: Wednesday, 30/Oct/2024 | ||
9:00am - 10:00am |
Keynote: Timo D. Hämäläinen Location: Amfi (1st floor) Chair: Jari Nurmi, Tampere University |
|
10:00am - 11:00am |
Optimization and tools for HW-implemented AI Location: Amfi (1st floor) Chair: Joachim Rodrigues, Lund University Towards a General Compilation Approach for On-device Training in Embedded Systems Karlsruhe Institute of Technology, Germany 10:20am - 10:40am Adaptive Quantization of Graph Convolutional Networks with Hardware-Aware On-device Training Linkoping University, Sweden 10:40am - 11:00am Leveraging Dynamic Range Analysis for Efficient Post-Training Quantization in Graph Convolutional Networks Linköping University, Sweden |
SoC and NoC Architecture Location: Danssalen (2nd floor) Chair: Jari Nurmi, Tampere University QoS-Aware Dynamic Voltage-Frequency Scaling for Mixed-Critical Systems based on Shielded Reinforcement Learning Technical University of Munich, Germany 10:20am - 10:40am Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis 1: Tallinn University of Technology, Estonia; 2: National Institute of Chemical Physics and Biophysics, Estonia 10:40am - 11:00am Improving Reliability in Network-on-Chip with Trust-based Adaptive Routing Approaches 1: Chair of Privacy and Security, Technische Universität Dresden, Germany; 2: Chair of Adaptive Dynamic Systems, Technische Universität Dresden, Germany; 3: Centre for Tactile Internet with Human-in-the-Loop (CeTI), Technische Universität Dresden, Germany |
11:00am - 11:40am |
Posters Day2 and Coffee Design Space Exploration of Dynamically Reconfigurable Network-on-Chip Architectures with Multiobjective Evolutionary Algorithms Technische Universität Dresden, Germany RV-ProViler: Evaluating RISC-V ISA for Application-Specific Requirements Technische Universität Dresden, Germany Design of a Karatsuba Multiplier to Accelerate Digital Signature Schemes on Embedded Systems Instituto de Microelectrónica de Sevilla (IMSE-CNM), CSIC-US, Seville, Spain High linear on-chip delay generator for a depth profiling CMOS SPAD Raman sensor University of Oulu, Finland A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces University of Kaiserslautern-Landau (RPTU), Germany Compact and Efficient Switching Power Amplifier for Micro-NMR Applications Linköping University, Sweden Joint CPU-FPGA Hardware-Aware Quantized Training of Graph Convolutional Networks Linköping University, Sweden FPGA-based Resource Efficient High Throughput Object Detection Using Pipelined CNN and Custom SSD Institute for Embedded Systems, University of Siegen, 57076 Siegen, Germany Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-Correction 1: IHP GmbH, Germany; 2: University of Potsdam, Germany; 3: Arquimea Research Center, Spain; 4: IPTC, ETSI Telecomunicacion, Universidad Politecnica de Madrid, Spain Quantitative Evaluation on the Limits of SORN Arithmetic Hardware Circuits 1: ITEM.me, University of Bremen, Bremen, Germany; 2: Hamburg University of Applied Sciences, Hamburg, Germany |
|
11:40am - 12:40pm |
Energy Harvesting Circuits Location: Danssalen (2nd floor) Chair: Victor Åberg, Lund University Analysis and Design of a Reconfigurable RF-DC Rectifier for RF Energy Harvesting Systems 1: Linkoping University, Sweden; 2: SAAB Group; 3: Aeronautics Institute of Technology - ITA 12:00pm - 12:20pm On the Optimal Design of Integrated AC-DC Converters for Energy Harvesting DEI, University of Padova, Italy 12:20pm - 12:40pm High-Sensitivity Hybrid Compensated RF-to-DC Converter for Low-Power RFEH Applications Linkoping University, Sweden |
Hardware accelerated AI applications Location: Amfi (1st floor) Chair: Atila Alvandpour, Linköping University Hardware Acceleration of Molecular Property Graph Prediction on a Heterogeneous Edge Platform 1: Linköping University, Sweden; 2: University of Texas at Dallas 12:00pm - 12:20pm Inter-node Communication in Multi-FPGA-based Computational Neuroscience Simulators: PHY-to-Link Chair of Integrated Digital Systems and Circuit Design (IDS), RWTH University, Germany 12:20pm - 12:40pm In-door Positioning using Distributed Massive MIMO: Architecture and FPGA Implementation Lund University, Sweden |
12:40pm - 1:40pm |
Lunch |
|
1:40pm - 2:40pm |
Keynote: Ted Johansson Location: Amfi (1st floor) Chair: Jussi Ryynänen, Aalto University |
|
2:40pm - 3:00pm |
Plenary3 Location: Amfi (1st floor) Chair: Jari Nurmi, Tampere University Multi-Stream FFT Architectures for a Distributed MIMO Large Intelligent Surfaces Testbed Linköping University, Sweden |
|
3:00pm - 3:40pm |
Posters Day2 and Coffee The same posters as on morning coffee. |
|
3:40pm - 4:20pm |
Plenary4 Location: Amfi (1st floor) Chair: Jari Nurmi, Tampere University Chair: Dag T. Wisland, UiO A 505 nW Programmable NanoController in 22 nm FDSOI-CMOS for Autonomous Ultra-Low-Power Mixed-Signal SoCs 1: Chair for Chip Design for Embedded Computing, TU Braunschweig, Germany; 2: Institute for CMOS Design, TU Braunschweig, Germany 4:00pm - 4:20pm ZuSE-KI-Mobil AI Chip Design Platform: An Overview 1: Technical University of Dresden; 2: Leibniz University Hannover; 3: Karlsruhe Institute of Technology; 4: Dream Chip Technologies GmbH; 5: Bayerische Motoren Werke Aktiengesellschaft (BMW AG); 6: Technical University of Munich; 7: Infineon Technologies AG Munich |
|
4:20pm - 4:40pm |
Awards and Closing Location: Amfi (1st floor) Chair: Jari Nurmi, Tampere University |
Contact and Legal Notice · Contact Address: Privacy Statement · Conference: IEEE NorCAS 2024 |
Conference Software: ConfTool Pro 2.6.152+TC © 2001–2025 by Dr. H. Weinreich, Hamburg, Germany |