Hardware-accelerated Compression Core on RISC-V for Online-BCG Data Reduction

Kazi Mohammad Abidur Rahman, Abdelrahman Noshy Abdelalim Ahmed, Goerschwin Fey, Ulf Kulau

Hamburg University of Technology, Germany

Implementation of the Tagged Geometric History Length Access Interval Predictor

Viktor Razilov¹, Emil Matúš¹, Gerhard Fettweis^1,2

¹Technische Universität Dresden, Germany; ²Barkhausen Institut, Dresden, Germany

On-chip READ and WRITE Circuits for Multi-bit Ferroelectric Tunnel Junction Memory

John Reuben¹, Suzanne Lancaster², Dietmar Fey¹, Stefan Slesazeck²

¹Friedrich-Alexander-Universität Erlangen-Nürnberg (FAU), Germany; ²NaMLab gGmbH

A Clock Duty Cycle Correction Circuitry for Ultra-Wide Frequency Range using Nested Loops

Raghavendra Rukmani Gowrishankar, Kamlesh Satyadev Singh, Milind Gopal Agrawal

Advanced Micro Devices

Design of Single-Bit Switched-Capacitor $\Delta\Sigma$ Modulators Employing Fast-Settling Techniques

Alessandro Catania, Francesco Gagliardi, Michele Dei

Department of Information Engineering - University of Pisa, Italy

Tywaves: A Typed Waveform Viewer for Chisel

Raffaele Meloni¹, H. Peter Hofstee^1,2, Zaid Al-Ars¹

¹Delft University of Technology, Delft, The Netherlands; ²IBM Infrastructure, Austin, Texas, US

Cycle Count Estimation of VLIW Processors Using Machine Learning

Kari Hepola¹, Jatan Shrestha², Joonas Multanen¹, Vivienne Wang², Joni Pajarinen², Pekka Jääskeläinen^1,3

¹Tampere University, Finland; ²Aalto University, Finland; ³Intel Finland Oy

FPGA-Based Hardware Acceleration for Deep Learning in Mobile Robotics

Yasir Al-Ameri, Minh Nguyen, Tomi Westerlund

University of Turku, Finland