Conference Agenda

Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).

 
 
Session Overview
Session
Posters Day2 and Coffee
Time:
Wednesday, 30/Oct/2024:
11:00am - 11:40am


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Presentations

Design Space Exploration of Dynamically Reconfigurable Network-on-Chip Architectures with Multiobjective Evolutionary Algorithms

Julian Haase, Najdet Charaf, Alexander Groß, Diana Göhringer

Technische Universität Dresden, Germany



RV-ProViler: Evaluating RISC-V ISA for Application-Specific Requirements

Muhammad Ali, Ensieh Aliagha, Mahmoud Elnashar, Diana Göhringer

Technische Universität Dresden, Germany



Design of a Karatsuba Multiplier to Accelerate Digital Signature Schemes on Embedded Systems

Pablo Navarro-Torrero, Eros Camacho-Ruiz, Macarena C. Martínez-Rodríguez, Piedad Brox

Instituto de Microelectrónica de Sevilla (IMSE-CNM), CSIC-US, Seville, Spain



High linear on-chip delay generator for a depth profiling CMOS SPAD Raman sensor

Belal Amin, Ilkka Nissinen

University of Oulu, Finland



A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces

Mohammadreza Esmaeilpour, Jan Lappas, Christian Weis, Norbert Wehn

University of Kaiserslautern-Landau (RPTU), Germany



Compact and Efficient Switching Power Amplifier for Micro-NMR Applications

Mohammed Al Shihabi, Natachai Terawatsakul, Alireza Saberkari

Linköping University, Sweden



Joint CPU-FPGA Hardware-Aware Quantized Training of Graph Convolutional Networks

Olle Hansson, Oscar Gustafsson, Jose Nunez-Yanez

Linköping University, Sweden



FPGA-based Resource Efficient High Throughput Object Detection Using Pipelined CNN and Custom SSD

Rashed Al Amin, Roman Obermaisser

Institute for Embedded Systems, University of Siegen, 57076 Siegen, Germany



Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-Correction

Oliver Schrape1, Anselm Breitenreiter1, Li Lu1, Marko Andjelkovic1, Ernesto Pun-Garcia3,4, Marisa Lopez-Vallejo4, Milos Krstic1,2

1IHP GmbH, Germany; 2University of Potsdam, Germany; 3Arquimea Research Center, Spain; 4IPTC, ETSI Telecomunicacion, Universidad Politecnica de Madrid, Spain



Quantitative Evaluation on the Limits of SORN Arithmetic Hardware Circuits

Moritz Bärthel1, Nils Hülsmeier1, Jochen Rust2, Steffen Paul1

1ITEM.me, University of Bremen, Bremen, Germany; 2Hamburg University of Applied Sciences, Hamburg, Germany



 
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