Conference Agenda

Overview and details of the sessions of this conference. Please select a date or location to show only sessions at that day or location. Please select a single session for detailed view (with abstracts and downloads if available).

 
Only Sessions at Location/Venue 
 
 
Session Overview
Location: Danssalen (2nd floor)
Date: Tuesday, 29/Oct/2024
11:40am
-
12:40pm
Efficient FPGA & ASIC designs
Location: Danssalen (2nd floor)
Chair: Peeter Ellervee, Tallinn University of Technology
 
11:40am - 12:00pm

Fully Automated Implementation of Reservoir Computing Models on FPGAs for Nanosecond Inference Times

Fabian Legl1, Jonas Kantic2

1: IFTA Ingenieurbuero fuer Thermoakustik GmbH, Germany; 2: Technical University of Munich, TUM School of Computation, Information and Technology, Department of Computer Engineering, Germany



12:00pm - 12:20pm

Exploiting SORN-Arithmetic for Efficient Cross Correlation in Low-Complexity FPGAs

Jochen Rust1, Marvin Henkel1, Nils Hülsmeier2, Moritz Bärthel2, Steffen Paul2

1: HAW Hamburg, Germany; 2: University of Bremen, Germany



12:20pm - 12:40pm

VLSI integration of a RO-based PUF into a 65 nm technology.

Pau Ortega-Castro, Felipe Rojas-Muñoz, Jose M. Mora-Gutiérrez, Piedad Brox, Macarena C. Martínez-Rodríguez

Instituto de Microelectrónica de Sevilla (CSIC-US), Spain

3:40pm
-
5:20pm
Transceiver Building Blocks
Location: Danssalen (2nd floor)
Chair: Ming Shen, Aalborg
 
3:40pm - 4:00pm

On the Efficiency Enhancement of Voltage Mode Digital Doherty Power Amplifiers

Edoardo Baiesi Fietta1, David Seebacher2, Davide Ponton2, Andrea Bevilacqua1

1: University of Padua, Italy; 2: Infineon Technologies Austria, Austria



4:00pm - 4:20pm

MMIC Design for Radiometer Receiver at 240 GHz in 0.13 μm SiGe BiCMOS Technology

Md Najmussadat1, Yehia Tawfik1, Raju Ahamed1, Mikko Varonen2, Dristy Parveg2, Antti Lamminen2, Pekka Pursula2, Kari Halonen1

1: Aalto University, Finland; 2: VTT Technical Research Centre of Finland



4:20pm - 4:40pm

A 0.00027mm2 1.2V 0.089pJ/bit 10Gbps 41.6GHz Standard-Cell-Based Passive-Less Wireless OOK Transmitter with On-Chip Antenna in 12nm FinFET

Hiroaki Kitaike1, Hironori Tagawa1, Masaya Kaneko2, Jin Nakamura2, Shufan Xu1, Ruilin Zhang1, Kunyang Liu1, Hiroki Wakatsuchi3, Kyoya Takano4, Hirofumi Shinohara1, Kiichi Niitsu1

1: Kyoto University, Japan; 2: Meitec Corp., Kyoto, Japan; 3: Nagoya Institute of Technology, Nagoya, Japan; 4: Tokyo University of Science, Tokyo, Japan



4:40pm - 5:00pm

Enhanced Mixer-First Receiver Using Series Switch N-Path Passive Mixer for Millimeter-Wave 5G Applications

Fatemeh Abbassi1,2, Timm Ostermann2, Christoph Wagner1

1: Silicon Austria Labs, Austria; 2: Johannes Kepler Universität Linz: JKU, Austria



5:00pm - 5:20pm

A 2Hz 1.2-2V 0.22-9nW 0.007mm2 65nm CMOS Down-Converter-Less Multiple-Output Clock Generator Using Stacked a Ring Oscillator and Frequency Dividers for Scaling-Friendly IoTs

You Wu1, Kei Awano1, Kento Okamura1, Teruaki Ono1, Kohei Sakamoto1, Hiroaki Kitaike1, Hironori Tagawa1, Jin Nakamura2, Masaya Kaneko2, Yuta Kimura3, Hiroaki Nakamura3, Shufan Xu1, Ruilin Zhang1, Kunyang Liu1, Hirofumi Shinohara1, Kiichi Niitsu1

1: Kyoto University, Japan; 2: Meitec Corporation, Kyoto, Japan; 3: Shuhari System, Fukuoka, Japan

Date: Wednesday, 30/Oct/2024
10:00am
-
11:00am
SoC and NoC Architecture
Location: Danssalen (2nd floor)
Chair: Jari Nurmi, Tampere University
 
10:00am - 10:20am

QoS-Aware Dynamic Voltage-Frequency Scaling for Mixed-Critical Systems based on Shielded Reinforcement Learning

Florian Maurer, Michael Meidinger, Yiming Lu, Thomas Hallermeier, Anmol Surhonne, Thomas Wild, Andreas Herkersdorf

Technical University of Munich, Germany



10:20am - 10:40am

Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis

Sergei Devadze1, Christine Elizabeth Nielsen2, Dmitri Mihhailov1, Peeter Ellervee1

1: Tallinn University of Technology, Estonia; 2: National Institute of Chemical Physics and Biophysics, Estonia



10:40am - 11:00am

Improving Reliability in Network-on-Chip with Trust-based Adaptive Routing Approaches

Sebastian Jaster1, Julian Haase2, Diana Göhringer2,3, Elke Franz1

1: Chair of Privacy and Security, Technische Universität Dresden, Germany; 2: Chair of Adaptive Dynamic Systems, Technische Universität Dresden, Germany; 3: Centre for Tactile Internet with Human-in-the-Loop (CeTI), Technische Universität Dresden, Germany

11:40am
-
12:40pm
Energy Harvesting Circuits
Location: Danssalen (2nd floor)
Chair: Victor Åberg, Lund University
 
11:40am - 12:00pm

Analysis and Design of a Reconfigurable RF-DC Rectifier for RF Energy Harvesting Systems

André Ponchet1,3, Javad Bagheri Asli1, Alireza Saberkari1, César Casañas1, Atila Alvandpour1, Ingemar Söderquist2, Osamu Saotome3

1: Linkoping University, Sweden; 2: SAAB Group; 3: Aeronautics Institute of Technology - ITA



12:00pm - 12:20pm

On the Optimal Design of Integrated AC-DC Converters for Energy Harvesting

Luca Bellemo, Giorgio Spiazzi, Andrea Bevilacqua

DEI, University of Padova, Italy



12:20pm - 12:40pm

High-Sensitivity Hybrid Compensated RF-to-DC Converter for Low-Power RFEH Applications

Wei Cao, Alireza Saberkari, Atila Alvandpour

Linkoping University, Sweden


 
Contact and Legal Notice · Contact Address:
Privacy Statement · Conference: IEEE NorCAS 2024
Conference Software: ConfTool Pro 2.6.153+TC
© 2001–2025 by Dr. H. Weinreich, Hamburg, Germany