An On-chip Digital Aging Sensor Circuit utilizing Leakage-current based Charge Accumulation

Kimiyoshi Usami, Mina Fukushima, Songxiang Wang, Kaito Nagai

Shibaura Institute of Technology, Japan

Novel Circuit for In-Memory Computing within STT-RAM Memory Blocks

Pegah Shafaghi, Yasser Rezaeiyan, Sonal Shreya, Farshad Moradi, Hooman Farkhani

Aarhus University, Denmark

A Systematic Comparison of Side-channel Countermeasures for RISC-V-based SoCs

Abolfazl Sajadi¹, Nusa Zidaric¹, Todor Stefanov¹, Nele Mentens^1,2

1: LIACS, Leiden University, Leiden, The Netherlands; 2: ES&S, COSIC, ESAT, KU Leuven, Leuven, Belgium

Processor Vulnerability Detection with the Aid of Assertions: RISC-V Case Study

Mohammad Reza Heidari Iman¹, Sallar Ahmadi-Pour², Rolf Drechsler^2,3, Tara Ghasempouri¹

1: Tallinn University of Technology; 2: University of Bremen; 3: Cyber-Physical Systems, DFKI GmbH

Towards modularity of the Rust RTIC real-time scheduling framework

Zakaria Madaoui¹, Henri Lunnikivi¹, Pawel Dzialo^1,2, Per Lindgren^2,1

1: Tampere University, Finland; 2: Luleå University of Technology, Sweden

Trustworthy Silicon: An MPSoC for a Secure Operating System

Sebastian Haas, Christopher Dunkel, Friedrich Pauls, Mattis Hasler, Yogesh Verma

Barkhausen Institut, Germany

AMPER-X: Adaptive Mixed-Precision RISC-V Core for Embedded Applications

Ahmad Othman, Ahmed Kamaleldin, Diana Göhringer

TU Dresden, Germany

Automated Intrinsic Support for ISA Extensions: Enhancing Software Generation for RISC-V and Beyond

Mayuri Bhadra^1,2, Stephanie Ecker^1,3, Daniel Albert¹, Ravindra Ramaiah¹, Sebastian Prebeck¹, Wolfgang Ecker^1,2

1: Infineon Technologies AG, Germany; 2: Technical University of Munich, Munich, Germany; 3: Chipglobe GmbH, Neubiberg, Germany

Fully Automatic Compiler Retargeting and CVX-IF Hardware Interface Generation for RISC-V Custom Instructions

Kari Hepola¹, Tharaka Ranasinghe Arachchige¹, Joonas Multanen¹, Pekka Jääskeläinen^1,2

1: Tampere University, Finland; 2: Intel Finland Oy

Hardware Solutions for Eliminating Context Switching Latency in Processor-Based Hard Real-Time Systems

Antti Nurmi, Abdesattar Kalache, Timo D. Hämäläinen

Tampere University, Finland

RISC-V Triplet: Tapeouts for Security Applications

Jonas Schupp¹, Patrick Karl¹, Jens Nöpel¹, Alexander Hepp¹, Tim Music¹, Georg Sigl^1,2

1: Technical University of Munich, Munich, Germany; 2: Fraunhofer Institute for Applied and Integrated Security (AISEC), Garching, Germany

Towards a General Compilation Approach for On-device Training in Embedded Systems

Iuliia Topko, Tanja Harbaum, Juergen Becker

Karlsruhe Institute of Technology, Germany

Adaptive Quantization of Graph Convolutional Networks with Hardware-Aware On-device Training

Jose Nunez-Yanez

Linkoping University, Sweden

Leveraging Dynamic Range Analysis for Efficient Post-Training Quantization in Graph Convolutional Networks

Hadi Mousanejad Jeddi, Mahdieh Grailoo, Jose Nunez-Yanez

Linköping University, Sweden

Hardware Acceleration of Molecular Property Graph Prediction on a Heterogeneous Edge Platform

Mahdieh Grailoo¹, Tooraj Nakoubin², Jose Nunez-Yanez¹

1: Linköping University, Sweden; 2: University of Texas at Dallas

Inter-node Communication in Multi-FPGA-based Computational Neuroscience Simulators: PHY-to-Link

Vida Sobhani, Jan Lorenz, Tobias Gemmeke

Chair of Integrated Digital Systems and Circuit Design (IDS), RWTH University, Germany

In-door Positioning using Distributed Massive MIMO: Architecture and FPGA Implementation

Dumitra Iancu, Lina Tinnerberg, Ove Edfors, Liang Liu

Lund University, Sweden

Multi-Stream FFT Architectures for a Distributed MIMO Large Intelligent Surfaces Testbed

Mikael Henriksson, Hugo Winbladh, Oscar Gustafsson

Linköping University, Sweden

A 505 nW Programmable NanoController in 22 nm FDSOI-CMOS for Autonomous Ultra-Low-Power Mixed-Signal SoCs

Moritz Weißbrich¹, Alexander Meyer², Adilet Dossanov², Vadim Issakov², Guillermo Payá-Vayá¹

1: Chair for Chip Design for Embedded Computing, TU Braunschweig, Germany; 2: Institute for CMOS Design, TU Braunschweig, Germany

ZuSE-KI-Mobil AI Chip Design Platform: An Overview

Shaown Mojumder¹, Simon Friedrich¹, Emil Matúš¹, Gerhard Fettweis¹, Matthias Lueders², Martin Friedrich², Oliver Renke², Holger Blume², Julian Hoefer³, Patrick Schmidt³, Juergen Becker³, Darius Grantz⁴, Markus Kock⁴, Jens Benndorf⁴, Nael Fasfous⁵, Pierpaolo Mori⁵, Hans-Joerg Voegel⁵, Samira Ahmadifarsani⁶, Leonidas Kontopoulos⁶, Ulf Schlichtmann⁶, Kay Bierzynski⁷

1: Technical University of Dresden; 2: Leibniz University Hannover; 3: Karlsruhe Institute of Technology; 4: Dream Chip Technologies GmbH; 5: Bayerische Motoren Werke Aktiengesellschaft (BMW AG); 6: Technical University of Munich; 7: Infineon Technologies AG Munich