Towards a General Compilation Approach for On-device Training in Embedded Systems

Iuliia Topko, Tanja Harbaum, Juergen Becker

Karlsruhe Institute of Technology, Germany

Adaptive Quantization of Graph Convolutional Networks with Hardware-Aware On-device Training

Jose Nunez-Yanez

Linkoping University, Sweden

Leveraging Dynamic Range Analysis for Efficient Post-Training Quantization in Graph Convolutional Networks

Hadi Mousanejad Jeddi, Mahdieh Grailoo, Jose Nunez-Yanez

Linköping University, Sweden

QoS-Aware Dynamic Voltage-Frequency Scaling for Mixed-Critical Systems based on Shielded Reinforcement Learning

Florian Maurer, Michael Meidinger, Yiming Lu, Thomas Hallermeier, Anmol Surhonne, Thomas Wild, Andreas Herkersdorf

Technical University of Munich, Germany

Architectural Solutions for High-Speed Data Processing Demands of CERN LHC Detectors with FPGA and High-Level Synthesis

Sergei Devadze¹, Christine Elizabeth Nielsen², Dmitri Mihhailov¹, Peeter Ellervee¹

1: Tallinn University of Technology, Estonia; 2: National Institute of Chemical Physics and Biophysics, Estonia

Improving Reliability in Network-on-Chip with Trust-based Adaptive Routing Approaches

Sebastian Jaster¹, Julian Haase², Diana Göhringer^2,3, Elke Franz¹

1: Chair of Privacy and Security, Technische Universität Dresden, Germany; 2: Chair of Adaptive Dynamic Systems, Technische Universität Dresden, Germany; 3: Centre for Tactile Internet with Human-in-the-Loop (CeTI), Technische Universität Dresden, Germany

Design Space Exploration of Dynamically Reconfigurable Network-on-Chip Architectures with Multiobjective Evolutionary Algorithms

Julian Haase, Najdet Charaf, Alexander Groß, Diana Göhringer

Technische Universität Dresden, Germany

RV-ProViler: Evaluating RISC-V ISA for Application-Specific Requirements

Muhammad Ali, Ensieh Aliagha, Mahmoud Elnashar, Diana Göhringer

Technische Universität Dresden, Germany

Design of a Karatsuba Multiplier to Accelerate Digital Signature Schemes on Embedded Systems

Pablo Navarro-Torrero, Eros Camacho-Ruiz, Macarena C. Martínez-Rodríguez, Piedad Brox

Instituto de Microelectrónica de Sevilla (IMSE-CNM), CSIC-US, Seville, Spain

High linear on-chip delay generator for a depth profiling CMOS SPAD Raman sensor

Belal Amin, Ilkka Nissinen

University of Oulu, Finland

A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces

Mohammadreza Esmaeilpour, Jan Lappas, Christian Weis, Norbert Wehn

University of Kaiserslautern-Landau (RPTU), Germany

Compact and Efficient Switching Power Amplifier for Micro-NMR Applications

Mohammed Al Shihabi, Natachai Terawatsakul, Alireza Saberkari

Linköping University, Sweden

Joint CPU-FPGA Hardware-Aware Quantized Training of Graph Convolutional Networks

Olle Hansson, Oscar Gustafsson, Jose Nunez-Yanez

Linköping University, Sweden

FPGA-based Resource Efficient High Throughput Object Detection Using Pipelined CNN and Custom SSD

Rashed Al Amin, Roman Obermaisser

Institute for Embedded Systems, University of Siegen, 57076 Siegen, Germany

Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-Correction

Oliver Schrape¹, Anselm Breitenreiter¹, Li Lu¹, Marko Andjelkovic¹, Ernesto Pun-Garcia^3,4, Marisa Lopez-Vallejo⁴, Milos Krstic^1,2

1: IHP GmbH, Germany; 2: University of Potsdam, Germany; 3: Arquimea Research Center, Spain; 4: IPTC, ETSI Telecomunicacion, Universidad Politecnica de Madrid, Spain

Quantitative Evaluation on the Limits of SORN Arithmetic Hardware Circuits

Moritz Bärthel¹, Nils Hülsmeier¹, Jochen Rust², Steffen Paul¹

1: ITEM.me, University of Bremen, Bremen, Germany; 2: Hamburg University of Applied Sciences, Hamburg, Germany

Analysis and Design of a Reconfigurable RF-DC Rectifier for RF Energy Harvesting Systems

André Ponchet^1,3, Javad Bagheri Asli¹, Alireza Saberkari¹, César Casañas¹, Atila Alvandpour¹, Ingemar Söderquist², Osamu Saotome³

1: Linkoping University, Sweden; 2: SAAB Group; 3: Aeronautics Institute of Technology - ITA

On the Optimal Design of Integrated AC-DC Converters for Energy Harvesting

Luca Bellemo, Giorgio Spiazzi, Andrea Bevilacqua

DEI, University of Padova, Italy

High-Sensitivity Hybrid Compensated RF-to-DC Converter for Low-Power RFEH Applications

Wei Cao, Alireza Saberkari, Atila Alvandpour

Linkoping University, Sweden

Hardware Acceleration of Molecular Property Graph Prediction on a Heterogeneous Edge Platform

Mahdieh Grailoo¹, Tooraj Nakoubin², Jose Nunez-Yanez¹

1: Linköping University, Sweden; 2: University of Texas at Dallas

Inter-node Communication in Multi-FPGA-based Computational Neuroscience Simulators: PHY-to-Link

Vida Sobhani, Jan Lorenz, Tobias Gemmeke

Chair of Integrated Digital Systems and Circuit Design (IDS), RWTH University, Germany

In-door Positioning using Distributed Massive MIMO: Architecture and FPGA Implementation

Dumitra Iancu, Lina Tinnerberg, Ove Edfors, Liang Liu

Lund University, Sweden

Multi-Stream FFT Architectures for a Distributed MIMO Large Intelligent Surfaces Testbed

Mikael Henriksson, Hugo Winbladh, Oscar Gustafsson

Linköping University, Sweden

A 505 nW Programmable NanoController in 22 nm FDSOI-CMOS for Autonomous Ultra-Low-Power Mixed-Signal SoCs

Moritz Weißbrich¹, Alexander Meyer², Adilet Dossanov², Vadim Issakov², Guillermo Payá-Vayá¹

1: Chair for Chip Design for Embedded Computing, TU Braunschweig, Germany; 2: Institute for CMOS Design, TU Braunschweig, Germany

ZuSE-KI-Mobil AI Chip Design Platform: An Overview

Shaown Mojumder¹, Simon Friedrich¹, Emil Matúš¹, Gerhard Fettweis¹, Matthias Lueders², Martin Friedrich², Oliver Renke², Holger Blume², Julian Hoefer³, Patrick Schmidt³, Juergen Becker³, Darius Grantz⁴, Markus Kock⁴, Jens Benndorf⁴, Nael Fasfous⁵, Pierpaolo Mori⁵, Hans-Joerg Voegel⁵, Samira Ahmadifarsani⁶, Leonidas Kontopoulos⁶, Ulf Schlichtmann⁶, Kay Bierzynski⁷

1: Technical University of Dresden; 2: Leibniz University Hannover; 3: Karlsruhe Institute of Technology; 4: Dream Chip Technologies GmbH; 5: Bayerische Motoren Werke Aktiengesellschaft (BMW AG); 6: Technical University of Munich; 7: Infineon Technologies AG Munich