Fault-Tolerant Character Recognition in Neuromorphic Systems Using RRAM Crossbar Arrays

Fatemeh Shirinzadeh¹, Abhoy Kole¹, Kamalika Datta^1,2, Saeideh Shirinzadeh^1,3, Rolf Drechsler^1,2

1: German Research Centre for Artificial Intelligence (DFKI), Germany; 2: Institute of Computer Science, University of Bremen, Germany; 3: Fraunhofer Institute for Systems and Innovation Research (ISI), Karlsruhe, Germany

Systematic Design of a PVT-Robust CMOS Time-Based-Controlled DC-DC Converter Using Open-Source Tools

Jorge Marin^1,2, Vicente Osorio¹, Andrés Martinez¹, Daniel Arévalos³, Krzysztof Herman⁴, Juan Pablo Martínez Brito⁵, Christian A. Rojas^1,2

1: Department of Electronic Eng., Universidad Tecnica Federico Santa Maria, Valparaiso, Chile; 2: Advanced Center of Electrical and Electronics Engineering, Universidad T´ecnica Federico Santa Mar´ıa; 3: Hochschule M¨unchen University of Applied Sciences, Munich, Germany; 4: IHP – Leibniz Institute for High Performance Microelectronics, Frankfurt (Oder), Germany; 5: CEITEC Semiconductores, Porto Alegre, Brazil

Memristor Differential Pair Ternary Weight Neural (TWN) Network Architecture

Yi Zhu, Dinesh Pamunuwa, Roshan Weerasekera

University of Bristol, United Kingdom

Simopt-Power: Leveraging Simulation Metadata For Low-Power Design Synthesis

Eashan Wadhwa, Shanker Shreejith

Trinity College Dublin, Ireland

EXAMINER: IP Extraction from MAGIC Logic-in-Memory using thermal side-channel attacks

Lorenzo Pfeifer, Antonia Weiler, Jeremy Scott Haas, Rainer Leupers, Jan Moritz Joseph

RWTH Aachen University, Germany

Evaluating Rapid Makespan Predictions for Heterogeneous Systems with Programmable Logic

Martin Wilhelm¹, Franz Freitag², Max Tzschoppe¹, Thilo Pionteck¹

1: Otto-von-Guericke University Magdeburg; 2: University of Applied Sciences Magdeburg-Stendal

KRS Unleashed: Towards a Robotics FPGA Development Environment for Rapid Prototyping

Paul Gottschaldt^1,2, Diana Goehringer^1,2

1: TU Dresden, Chair of Adaptive Dynamic Systems, Germany; 2: TU Dresden, Centre for Tactile Internet with Human-in-the-Loop (CeTI), Dresden, Germany

A Hierarchical Approach to Health Management in Heterogeneous Embedded Systems

Anton Tsertov¹, Sergei Devadze², Artur Jutman², Konstantin Shibin¹

1: Tallinn University of Technology, Estonia; 2: Testonica Lab

Towards Achieving Vertical Reuse in SoC-level Verification

Petr Bardonek¹, Alessandra Dolmeta², Marcela Zachariasova¹, Guido Masera²

1: Brno University of Technology, Czech Republic; 2: Politecnico di Torino

A Robust, Fully Integrated 30.5-33.2GHz and 34.3-36.8GHz Frequency Synthesizer in SiGe-BiCMOS for Space Applications

Frank Herzel, Seyyid Dilek, Jakub Jablonski, Falk Korndoerfer, Corrado Carta, Gunter Fischer

IHP Frankfurt (Oder)

A Foreground Calibration Scheme for Comparator Offsets in Loop-Unrolled SAR ADCs

Shaobai Xing, Pietro Andreani, Wenbo Li

lund university, Sweden

A Low-Voltage Class-AB CDTA with Ultra-Low Input Resistance and Extended Linear Range

Astha Dadheech, Nikhil Raj, Divyang Rawal

The LNMIIT,jaipur, India

A 0.9 V StrongARM Latch Comparator with 16 ps Delay and 7.5 fJ/op in 16 nm FinFET CMOS Technology

Rafael Ferreira¹, Subrahmanyam Boyapati², Rao Bandi², Miguel Coelho³, Rafael Martins¹, Alexandra Matos¹, Pedro Toledo², Luis Oliveira^1,4,5,6, José Augusto^3,4, João Oliveira^1,4,5,6

1: NOVA School of Science and Engineering, Portugal; 2: Synopys; 3: Faculty of Sciences of the University of Lisbon, Portugal; 4: Center of Technology and Systems (CTS-UNINOVA); 5: Institute of Systems and Computer Engineering - Research and Development (INESC-ID); 6: Department of Electrical and Computer Engineering (DEEC)

A Low-Power and High-Precision Winner-Take-All Circuit for Low-Voltage Applications

Mehdi Saberi¹, Fahimeh Rahimi², Alexandre Schmid¹

1: Swiss Federal Institute of Technology Lausanne (EPFL), Switzerland; 2: Ferdwosi University of Mashhad, Iran

Time-resolved single-photon counting IC for Raman Imaging

Leeladhar Bodu, Tuomo Talala, Jan Nissinen, Ilkka Nissinen

Circuits and Systems (CAS) research unit, University of Oulu, Finland

300mV-VDD, nW-Power, ST-DIGOTA using I/O Devices in FinFET Technology

Alexandra Matos³, Ricardo Machado^2,3, Pedro Toledo², Miguel Coelho¹, Rafael Ferreira³, Rafael Martins³, Boyapati Subrahmanyam², João Oliveira³, Luís Oliveira³, José Augusto^1,4

1: Faculty of Sciences of the University of Lisbon, Portugal; 2: Synopsys; 3: Department of Electrical and Computer Engineering (DEEC), NOVA School of Science and Technology, Center of Technology and Systems (CTS-UNINOVA), Associated Laboratory of Intelligent Systems (LASI), 2829-516 Lisbon, Portugal; 4: nstitute of Systems and Computer Engineering - Research and Development (INESC-ID)

GenIE: Reuse-Oriented Generation of Domain-Specific Instruction Extensions

Philipp van Kempen¹, Andreas Hager-Clukas², Daniel Mueller-Gritschneder³, Ulf Schlichtmann¹

1: Technical University of Munich, Germany; 2: Hochschule München, Germany; 3: TU Wien, Austria

Performance Evaluation of MAGIC-ReRAM Arithmetic Circuits for Low-Latency In-Memory Computing

Saeideh Nabipour¹, Fatemeh Shirinzadeh¹, Kamalika Datta^1,2, Abhoy Kole¹, Saeideh Shirinzadeh^1,3, Rolf Drechsler^1,2

1: Cyber-Physical Systems, DFKI GmbH, Germany; 2: University of Bremen, Germany; 3: Fraunhofer Institute for Systems and Innovation Research (ISI), Karlsruhe, Germany

Novel Verification IP (VIP) for AXI4 interconnects employing Universal Verification Methodology (UVM)

Petri Sydänmaa¹, Jaisal Ashraf¹, Mohsin Abbas²

1: Nokia Networks and Solutions, Finland; 2: Faculty of Information Technology and Communication Sciences, Tampere University

4T Bitcell for Digital Compute-in-Memory

Florian Freye, Christian Lanius, Nils Mutert, Tobias Gemmeke

Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen, Germany

Rust for Safety and Security Critical Systems

Malte Munch¹, Marcus Lindner², Johan Eriksson³, Pawel Dzialo¹, Per Lindgren¹

1: Luleå University of Technology, Sweden; 2: Scania AB, Sweden; 3: Grepit AB, Sweden

Model-Driven Generation of Executable Models for Hardware Specification Validation

Robert Kunzelmann^1,2, Raymund Tonyka^1,2, Vinod Bangalore Ganesh^1,3, Raphael Kunz^1,2, Stephanie Ecker^1,4, Wolfgang Ecker^1,2

1: Infineon Technologies AG, Germany; 2: Technical University of Munich, Germany; 3: Technical University of Dresden, Germany; 4: Chipglobe GmbH, Germany

HyPPA: PPA-Aware Hierarchical RTL Generation and Evaluation of RISC-V Cores Using Hyperparameter Tuning

Mohamed Badawy^1,2, Jiulong Wang^1,2, Vijaydeep Yadav¹, Nguyen Anh Vu Doan¹, Paritosh Kumar Sinha¹, Wolfgang Ecker^1,2

1: Infineon Technologies AG; 2: Technical University of Munich

ChiselTrace: Typed Behavioral Debugging in Chisel Through Signal Dependency Tracing

Jarl Brand¹, Casper Cromjongh¹, Peter Hofstee^1,2, Zaid Al-Ars¹

1: Delft University of Technology, The Netherlands; 2: IBM Infrastructure, Austin, TX, US

A 8.9 μW 12.3-ENOB SAR ADC with <1 LSB DNL/INL for Electrochemical Impedance Spectroscopy in 12 nm CMOS

Christian Ziegler¹, Alexander Meyer¹, Fa Foster Dai², Liubov Bakhchova¹, Vadim Issakov¹

1: TU Braunschweig, Germany; 2: Guest Professor, TU Braunschweig, Germany

Design and Experimental Verification of A 0.14-0.55V 1.9-24.2pW 22nm 3-bit Binary Search Supply-to-Digital Converter Using One-Hot Hard-Wired Topology and Supply-Dependent-Activation Buffers for Supply Sensing IoT Systems

Hiroaki Kitaike¹, Hironori Tagawa¹, Kento Okamura¹, Wu You¹, Kei Awano¹, Jin Nakamura², Masaya Kaneko², Yuta Kimura³, Hiroaki Nakamura³, Shufan Xu¹, Kunyang Liu¹, Hirofumi Shinohara¹, Kiichi Niitsu¹

1: Kyoto University, Japan; 2: Meitec Corp, Japan; 3: Shuharisystem Corp, Japan

Automatic Reference Clock Duty Cycle Calibration System for Dual Edge Sampling RF Circuits

Miikka Tenhunen^1,2, Veeti Lahtinen^1,2, Marko Kosunen¹

1: Aalto University; 2: Saab Finland Oy

A 50Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130nm SiGe:C BiCMOS Technology

Mohammed Iftekhar, Babak Sadiye, Wolfgang Mueller, J. Christoph Scheytt

Heinz Nixdorf Institute, Paderborn University, Germany

FPGA Acceleration of Convolutional Neural Networks at the Edge: A Comparative Study on High-Level Synthesis Frameworks

João Faria^1,2, Fabio Coutinho^1,2, Arnaldo Oliveira^1,2

1: Universidade de Aveiro, Portugal; 2: Instituto de Telecomunicações, Aveiro

Improving AI Accelerator Performance Through Co-Designing Neural Networks and Systolic Hardware

Annina Gutermann, Alexey Serdyuk, Foivos Paraskevas, Hella Toto Kiesa, Fabian Lesniak, Jakob Schwarz, Michael Hartmann, Tanja Harbaum, Juergen Becker

Karlsruhe Institute of Technology, Germany

Implementation Study of a Noise Cancellation Filter for a 0–3 MASH Delta-Sigma-ADC

Jonathan Ungethüm, Nicolas Graber, Simon Wilhelmstätter, John G. Kauffman, Maurits Ortmanns

Institute of Microelectronics, University of Ulm, Germany

ATAS-HM: Adaptive Task Allocation for Real-Time Tasks on Heterogeneous Multicore Systems

Arthur Nathaniel Mwang’onda, Diana Goehringer

TUD Dresden University of Technology

An Adaptive and Secure Resource Management Architecture for Virtualized FPGAs

Zuwen Ou^1,2, Lu Jiang¹, Lester Kalms^1,2, Diana Göhringer^1,3

1: TU Dresden, Chair of Adaptive Dynamic Systems, Germany; 2: Deutsche Zentrum für Astrophysik, Postplatz 1, 02826 Görlitz, Germany; 3: TU Dresden, Centre for Tactile Internet with Human-in-the-Loop (CeTI), Germany

Post-Loaded Substrate-Integrated Waveguide Filter With Liquid Crystal-Based Frequency Tuning Operating at 6G Band

Sangjun Oh^1,2, Sehwan Choi¹, Seunggoo Nam¹, Boyoung Lee¹, Hojoon Lee¹, Juseop Lee²

1: Korea Electronics Technology Institute, Korea, Republic of (South Korea); 2: Korea University, Korea, Republic of (South Korea)

A Robust 90-nW Power-On Reset Circuit with Brown-Out Detection for RF Energy-Harvesting

Patrick Fath¹, Harald Pretl²

1: Johannes Kepler University Linz, Austria; 2: Johannes Kepler University Linz, Austria

Delay-Switching Oscillator and Switching-Mode Power Amplifier in 65 nm CMOS for Isolation Crossing SWIPT

Lukas Huessen, Muh-Dey Wei, Renato Negra

HFE RWTH Aachen, Germany

A 28-GHz Monostatic OFDM-based ISAC System on RFSoC with Real-time Processing

Yizheng Wu¹, Arif Rahmadian Arifianto², Vishnu Unnikrishnan¹, Anteneh Atumo Gebremariam³, Liang Liu²

1: Tampere University, Finland; 2: Lund University, Sweden; 3: Ericsson AB, Sweden

Hardware Accelerated Synthetic X-ray Medical Image Generation Using HBM-based FPGAs

Sam Aanhane¹, Per Knobs², Rob de Jong², Casper Cromjongh¹, Zaid Al-Ars¹

1: Delft University of Technology, Delft, Netherlands; 2: Philips Medical Systems, Best, Netherlands

System Level Acceleration of Banded Smith Waterman on FPGA

Christian Lanius, Ibrahim Burak Yorulmaz, Tobias Gemmeke

RWTH Aachen University, Germany

Grading Defects: Evaluating Approximate Circuits for Error-Tolerant Systems

Gianluca Martino¹, Alberto Garcia-Ortiz², Lutz Schammer¹, Goerschwin Fey¹

1: Hamburg University of Technology, Germany; 2: University of Bremen

Near-Threshold Voltage Massive MIMO Computing

Mikael Rinkinen¹, Mehdi Safarpour¹, Shahriah Shahabuddin², Olli Silvén¹, Lauri Koskinen¹

1: University of Oulu, Finland; 2: Oklahoma State University, USA

Exploration of Short Floating-Point Numbers for Hardware-Friendly Digital Predistortion

Ziyi Yu, Talemwa Mubanda, Per Larsson-Edefors

Chalmers University of Technology, Sweden

The PAE Cell: A Novel Multiple Outputs Logic Cell and Technology Mapping for eFPGA

Ryo Iwasaki, Kenshu Seto, Masahiro Iida

Kumamoto University, Japan

Towards Predictable Ultra-Low Latency End-Nodes with Hardware-Accelerated Abstract Timers

Antti Nurmi¹, Henri Lunnikivi¹, Per Lindgren^1,2, Timo D. Hämäläinen¹

1: Tampere University, Finland; 2: Luleå University of Technology, Sweden

Lightweight Multicast Interconnect for Time-Predictable Data Streams in MPSoCs

Maximilian Kirschner¹, Henrik Scheidt², Jürgen Becker²

1: FZI Research Center for Information Technology, Germany; 2: Karlsruhe Institute of Technology, Germany

An Ultra-low Power Bandpass Filter Bank with Input and Output Common-Mode Feedback in FD-SOI

Damian Panter^1,2, Gabriel Lías Villar¹, Erkan Nevzat Isa¹, Amelie Hagelauer^1,2

1: Department of Circuits and Systems, Fraunhofer Research Institution for Microsystems and Solid State Technologies EMFT, Munich, Germany; 2: Chair of Micro- and Nanosystems, Technical University of Munich, Munich, Germany

Integrated Electroforming of Memristor Cells in Crossbar Arrays

Ricardo Heinen, Jonas Zoche, Ralf Wunderlich, Stefan Heinen

RWTH Aachen University, Germany

A 1.4V 260pW 1mm2 65nm CMOS Temperature/pH Sensing IC Featuring Voltage-Stacking Timer and Wireless Transmitter for Stomach-Acid-Charged Tablet-Type Digital Pills with Long-Term In-Body Monitoring

You Wu¹, Kei Awano¹, Ikuro Yamane², Hiroaki Kitaike³, Masaya Kaneko³, Hisataka Maruyama⁴, Hiroshi Miyaguchi⁵, Shinya Yoshida⁵, Takumi Kobayashi⁶, Daisuke Anzai⁶, Takeshi Fujiyabu⁷, Natsuko Inagaki⁷, Kenji Takeda⁷, Toshiro Yamanaka⁷, Taichi Ito⁷, Hiroki Kawashima⁴, Mitsuhiro Fujishiro⁷, Fumihito Arai⁷, Koji Ohnishi², Kiichi Niitsu⁷

1: Kyoto University, Kyoto, Japan; 2: Otsuka Pharmaceutical Co., Ltd., Tokyo, Japan; 3: Meitec Corp., Kyoto, Japan; 4: Nagoya University, Nagoya, Japan; 5: Shibaura Institute of Technology, Tokyo, Japan; 6: Osaka Metropolitan University, Osaka, Japan; 7: The University of Tokyo, Tokyo, Japan

Implementation of Drive Signal in DC-DC Converters for Chaos Synchronization

Daniils Surmacs, Sergejs Tjukovs, Romans Kusnins, Kristaps Gailis, Dmitrijs Pikulins

Riga Technical University, Latvia

Accurate Analysis of Switching Transients in the High-Frequency, Integrated Dual-Path Step-Down DC-DC Converter

Domenico Frassetto¹, Stefano Cabizza², Asif Karim³, Giorgio Spiazzi¹, Andrea Bevilacqua¹, Andrea Neviani¹

1: University of Padova, Italy; 2: Infineon Technologies Italia S.r.l.; 3: Infineon Technologies Austria AG

A Power-Efficient Analog Integrated Neural Network for Multiple Sclerosis Disease Detection

Vassilis Alimisis¹, Konstantinos Cheliotis², Vasileios Moustakas², Anna Mylona², Andreas Papathanasiou², Paul P. Sotiriadis²

1: Archimedes, Athena Research Center, Greece; 2: National Technical University of Athens, Greece

Exploiting multi-VT FDSOI technology for improved area and energy trade-offs for ultra-low voltage Schmitt Triggers

Louisa Charlotte Nägle¹, Snorre Aunet², Ulrich Rückert¹

1: Bielefeld University, Germany; 2: Norwegian Universityof Science and Technology, Norway

Matrix-Vectorized Canonical Signed Digit Quantized Neural Networks for Efficient Forward Pass Simulation

Maria Khan, Jari Nurmi

Tampere University, Finland

Automatic Verification of Analog and Mixed-Signal Neural Network Accelerators and Matrix Multipliers

Roland Müller¹, Bijoy Kundu¹, Jan Maximilian Vieregge¹, Yogesh Patil¹, Ralf Brederlow²

1: Fraunhofer Institut for Integrated Circuits IIS, Germany; 2: Technical University of Munich, Germany

Efficient Prompt Design for Resource-Constraint Deployment of Local LLMs

Aisvarya Adeseye, Jouni Isoaho, Seppo Virtanen, Mohammad Tahir

university of Turku, Finland

Small Packets, Big Challenges: Enhancing Reliability in High-Speed, Low-Latency Inter-FPGA Communication

Vida Sobhani, Jialan Zheng, Tobias Gemmeke

RWTH Aachen, Germany

A Novel Layout–Circuit Co-Design Framework for Radiation Hardening in Nanoscale Technology

Aobo Cui, Eleonora Vacca, Luca Sterpone, Sarah Azimi

Politecnico di Torino, Italy

A (145,128) DEC-TED BCH Decoder with Composite Field and Redundant Arithmetic

Hossein Hashemi Shadmehri, Christian Lanius, Tobias Gemmeke

Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen University

Optimizing Embedded Software Platform Development: A Multi-Stage MDA-Driven Approach to Firmware Generation for Multiple Programming Languages

Raphael Kunz^1,2, Lijun Chen^1,2, Stephanie Ecker^1,3, Yash Ranjan¹, Paritosh Kumar Sinha¹, Wolfgang Ecker^1,2

1: Infineon Technologies AG; 2: Technical University of Munich, Germany; 3: ChipGlobe GmbH

Thoth: Rust-Driven Firmware and HDL Co-Design for Trusted IoT/UAV Systems

Mohamed El-Hadedy¹, Wen-Mei Hwu²

1: California Polytechnic University, United States of America; 2: UIUC, USA

All About Nothing: Towards Zero-Cost Hardware Accelerated RISC-V Interrupt Handling in Rust

Pawel Dzialo, Per Lindgren

Luleå Tekniska Universitet, Sweden

A 22nm Coarse-Grained Reconfigurable Array with Novel Features for Machine Learning and Digital Signal Processing

Waqar Hussain¹, Alexandra Geciova¹, Ralf Hekmann¹, Henry Hoffmann², Zohaib Hassan³, Jari Nurmi³

1: Nordic Semiconductor ASA, Norway; 2: Department of Computer Science, The University of Chicago, Chicago, IL, USA; 3: Wireless Research Centre, Tampere University, Tampere, Finland

A 4-W Ka-Band High Efficiency 0.15 μm GaAs Stacked Power Amplifier Design

Batuhan Dinc, Mustafa Berke Yelten

Istanbul Technical University, Turkiye