Conference Agenda

4:00pm - 4:20pm

Model-Driven Generation of Executable Models for Hardware Specification Validation

Robert Kunzelmann^1,2, Raymund Tonyka^1,2, Vinod Bangalore Ganesh^1,3, Raphael Kunz^1,2, Stephanie Ecker^1,4, Wolfgang Ecker^1,2

¹Infineon Technologies AG, Germany; ²Technical University of Munich, Germany; ³Technical University of Dresden, Germany; ⁴Chipglobe GmbH, Germany

4:20pm - 4:40pm

HyPPA: PPA-Aware Hierarchical RTL Generation and Evaluation of RISC-V Cores Using Hyperparameter Tuning

Mohamed Badawy^1,2, Jiulong Wang^1,2, Vijaydeep Yadav¹, Nguyen Anh Vu Doan¹, Paritosh Kumar Sinha¹, Wolfgang Ecker^1,2

¹Infineon Technologies AG; ²Technical University of Munich

4:40pm - 5:00pm

ChiselTrace: Typed Behavioral Debugging in Chisel Through Signal Dependency Tracing

Jarl Brand¹, Casper Cromjongh¹, Peter Hofstee^1,2, Zaid Al-Ars¹

¹Delft University of Technology, The Netherlands; ²IBM Infrastructure, Austin, TX, US