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Digital: Tools and Methodologies
Time:
Tuesday, 28/Oct/2025:
4:00pm - 5:00pm
Session Chair: Goerschwin Fey , TU Hamburg
Presentations
4:00pm - 4:20pm Model-Driven Generation of Executable Models for Hardware Specification Validation
Robert Kunzelmann 1,2 , Raymund Tonyka1,2 , Vinod Bangalore Ganesh1,3 , Raphael Kunz1,2 , Stephanie Ecker1,4 , Wolfgang Ecker1,2
1 Infineon Technologies AG, Germany; 2 Technical University of Munich, Germany; 3 Technical University of Dresden, Germany; 4 Chipglobe GmbH, Germany
4:20pm - 4:40pm HyPPA: PPA-Aware Hierarchical RTL Generation and Evaluation of RISC-V Cores Using Hyperparameter Tuning
Mohamed Badawy 1,2 , Jiulong Wang1,2 , Vijaydeep Yadav1 , Nguyen Anh Vu Doan1 , Paritosh Kumar Sinha1 , Wolfgang Ecker1,2
1 Infineon Technologies AG; 2 Technical University of Munich
4:40pm - 5:00pm ChiselTrace: Typed Behavioral Debugging in Chisel Through Signal Dependency Tracing
Jarl Brand 1 , Casper Cromjongh1 , Peter Hofstee1,2 , Zaid Al-Ars1
1 Delft University of Technology, The Netherlands; 2 IBM Infrastructure, Austin, TX, US