Conference Agenda

Memristor Differential Pair Ternary Weight Neural (TWN) Network Architecture

Yi Zhu, Dinesh Pamunuwa, Roshan Weerasekera

University of Bristol, United Kingdom

Simopt-Power: Leveraging Simulation Metadata For Low-Power Design Synthesis

Eashan Wadhwa, Shanker Shreejith

Trinity College Dublin, Ireland

EXAMINER: IP Extraction from MAGIC Logic-in-Memory using thermal side-channel attacks

Lorenzo Pfeifer, Antonia Weiler, Jeremy Scott Haas, Rainer Leupers, Jan Moritz Joseph

RWTH Aachen University, Germany

Evaluating Rapid Makespan Predictions for Heterogeneous Systems with Programmable Logic

Martin Wilhelm¹, Franz Freitag², Max Tzschoppe¹, Thilo Pionteck¹

¹Otto-von-Guericke University Magdeburg; ²University of Applied Sciences Magdeburg-Stendal

KRS Unleashed: Towards a Robotics FPGA Development Environment for Rapid Prototyping

Paul Gottschaldt^1,2, Diana Goehringer^1,2

¹TU Dresden, Chair of Adaptive Dynamic Systems, Germany; ²TU Dresden, Centre for Tactile Internet with Human-in-the-Loop (CeTI), Dresden, Germany

A Hierarchical Approach to Health Management in Heterogeneous Embedded Systems

Anton Tsertov¹, Sergei Devadze², Artur Jutman², Konstantin Shibin¹

¹Tallinn University of Technology, Estonia; ²Testonica Lab

Towards Achieving Vertical Reuse in SoC-level Verification

Petr Bardonek¹, Alessandra Dolmeta², Marcela Zachariasova¹, Guido Masera²

¹Brno University of Technology, Czech Republic; ²Politecnico di Torino

A Robust, Fully Integrated 30.5-33.2GHz and 34.3-36.8GHz Frequency Synthesizer in SiGe-BiCMOS for Space Applications

Frank Herzel, Seyyid Dilek, Jakub Jablonski, Falk Korndoerfer, Corrado Carta, Gunter Fischer

IHP Frankfurt (Oder)

A Foreground Calibration Scheme for Comparator Offsets in Loop-Unrolled SAR ADCs

Shaobai Xing, Pietro Andreani, Wenbo Li

lund university, Sweden

A Low-Voltage Class-AB CDTA with Ultra-Low Input Resistance and Extended Linear Range

Astha Dadheech, Nikhil Raj, Divyang Rawal

The LNMIIT,jaipur, India

A 0.9 V StrongARM Latch Comparator with 16 ps Delay and 7.5 fJ/op in 16 nm FinFET CMOS Technology

Rafael Ferreira¹, Subrahmanyam Boyapati², Rao Bandi², Miguel Coelho³, Rafael Martins¹, Alexandra Matos¹, Pedro Toledo², Luis Oliveira^1,4,5,6, José Augusto^3,4, João Oliveira^1,4,5,6

¹NOVA School of Science and Engineering, Portugal; ²Synopys; ³Faculty of Sciences of the University of Lisbon, Portugal; ⁴Center of Technology and Systems (CTS-UNINOVA); ⁵Institute of Systems and Computer Engineering - Research and Development (INESC-ID); ⁶Department of Electrical and Computer Engineering (DEEC)