Conference Agenda

Session

SoC: Design and Verification

Time:

Tuesday, 28/Oct/2025:

11:40am - 12:40pm

Session Chair: Peeter Ellervee, Tallinn University of Technology

Location: Room 108

Zunda krastmala 8

Presentations

11:40am - 12:00pm

GenIE: Reuse-Oriented Generation of Domain-Specific Instruction Extensions

Philipp van Kempen¹, Andreas Hager-Clukas², Daniel Mueller-Gritschneder³, Ulf Schlichtmann¹

¹Technical University of Munich, Germany; ²Hochschule München, Germany; ³TU Wien, Austria

12:00pm - 12:20pm

Performance Evaluation of MAGIC-ReRAM Arithmetic Circuits for Low-Latency In-Memory Computing

Saeideh Nabipour¹, Fatemeh Shirinzadeh¹, Kamalika Datta^1,2, Abhoy Kole¹, Saeideh Shirinzadeh^1,3, Rolf Drechsler^1,2

¹Cyber-Physical Systems, DFKI GmbH, Germany; ²University of Bremen, Germany; ³Fraunhofer Institute for Systems and Innovation Research (ISI), Karlsruhe, Germany

12:20pm - 12:40pm

Novel Verification IP (VIP) for AXI4 interconnects employing Universal Verification Methodology (UVM)

Petri Sydänmaa¹, Jaisal Ashraf¹, Mohsin Abbas²

¹Nokia Networks and Solutions, Finland; ²Faculty of Information Technology and Communication Sciences, Tampere University