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SoC: Design and Verification
Time:
Tuesday, 28/Oct/2025:
11:40am - 12:40pm
Session Chair: Peeter Ellervee , Tallinn University of Technology
Presentations
11:40am - 12:00pm GenIE: Reuse-Oriented Generation of Domain-Specific Instruction Extensions
Philipp van Kempen1 , Andreas Hager-Clukas2 , Daniel Mueller-Gritschneder3 , Ulf Schlichtmann1
1 Technical University of Munich, Germany; 2 Hochschule München, Germany; 3 TU Wien, Austria
12:00pm - 12:20pm Performance Evaluation of MAGIC-ReRAM Arithmetic Circuits for Low-Latency In-Memory Computing
Saeideh Nabipour 1 , Fatemeh Shirinzadeh1 , Kamalika Datta1,2 , Abhoy Kole1 , Saeideh Shirinzadeh1,3 , Rolf Drechsler1,2
1 Cyber-Physical Systems, DFKI GmbH, Germany; 2 University of Bremen, Germany; 3 Fraunhofer Institute for Systems and Innovation Research (ISI), Karlsruhe, Germany
12:20pm - 12:40pm Novel Verification IP (VIP) for AXI4 interconnects employing Universal Verification Methodology (UVM)
Petri Sydänmaa1 , Jaisal Ashraf1 , Mohsin Abbas 2
1 Nokia Networks and Solutions, Finland; 2 Faculty of Information Technology and Communication Sciences, Tampere University