Post-Loaded Substrate-Integrated Waveguide Filter With Liquid Crystal-Based Frequency Tuning Operating at 6G Band

Sangjun Oh^1,2, Sehwan Choi¹, Seunggoo Nam¹, Boyoung Lee¹, Hojoon Lee¹, Juseop Lee²

1: Korea Electronics Technology Institute, Korea, Republic of (South Korea); 2: Korea University, Korea, Republic of (South Korea)

A Robust 90-nW Power-On Reset Circuit with Brown-Out Detection for RF Energy-Harvesting

Patrick Fath¹, Harald Pretl²

1: Johannes Kepler University Linz, Austria; 2: Johannes Kepler University Linz, Austria

Delay-Switching Oscillator and Switching-Mode Power Amplifier in 65 nm CMOS for Isolation Crossing SWIPT

Lukas Huessen, Muh-Dey Wei, Renato Negra

HFE RWTH Aachen, Germany

A 28-GHz Monostatic OFDM-based ISAC System on RFSoC with Real-time Processing

Yizheng Wu¹, Arif Rahmadian Arifianto², Vishnu Unnikrishnan¹, Anteneh Atumo Gebremariam³, Liang Liu²

1: Tampere University, Finland; 2: Lund University, Sweden; 3: Ericsson AB, Sweden

Hardware Accelerated Synthetic X-ray Medical Image Generation Using HBM-based FPGAs

Sam Aanhane¹, Per Knobs², Rob de Jong², Casper Cromjongh¹, Zaid Al-Ars¹

1: Delft University of Technology, Delft, Netherlands; 2: Philips Medical Systems, Best, Netherlands

System Level Acceleration of Banded Smith Waterman on FPGA

Christian Lanius, Ibrahim Burak Yorulmaz, Tobias Gemmeke

RWTH Aachen University, Germany

Grading Defects: Evaluating Approximate Circuits for Error-Tolerant Systems

Gianluca Martino¹, Alberto Garcia-Ortiz², Lutz Schammer¹, Goerschwin Fey¹

1: Hamburg University of Technology, Germany; 2: University of Bremen

Near-Threshold Voltage Massive MIMO Computing

Mikael Rinkinen¹, Mehdi Safarpour¹, Shahriah Shahabuddin², Olli Silvén¹, Lauri Koskinen¹

1: University of Oulu, Finland; 2: Oklahoma State University, USA

Exploration of Short Floating-Point Numbers for Hardware-Friendly Digital Predistortion

Ziyi Yu, Talemwa Mubanda, Per Larsson-Edefors

Chalmers University of Technology, Sweden

The PAE Cell: A Novel Multiple Outputs Logic Cell and Technology Mapping for eFPGA

Ryo Iwasaki, Kenshu Seto, Masahiro Iida

Kumamoto University, Japan

Towards Predictable Ultra-Low Latency End-Nodes with Hardware-Accelerated Abstract Timers

Antti Nurmi¹, Henri Lunnikivi¹, Per Lindgren^1,2, Timo D. Hämäläinen¹

1: Tampere University, Finland; 2: Luleå University of Technology, Sweden

Lightweight Multicast Interconnect for Time-Predictable Data Streams in MPSoCs

Maximilian Kirschner¹, Henrik Scheidt², Jürgen Becker²

1: FZI Research Center for Information Technology, Germany; 2: Karlsruhe Institute of Technology, Germany

An Ultra-low Power Bandpass Filter Bank with Input and Output Common-Mode Feedback in FD-SOI

Damian Panter^1,2, Gabriel Lías Villar¹, Erkan Nevzat Isa¹, Amelie Hagelauer^1,2

1: Department of Circuits and Systems, Fraunhofer Research Institution for Microsystems and Solid State Technologies EMFT, Munich, Germany; 2: Chair of Micro- and Nanosystems, Technical University of Munich, Munich, Germany

Integrated Electroforming of Memristor Cells in Crossbar Arrays

Ricardo Heinen, Jonas Zoche, Ralf Wunderlich, Stefan Heinen

RWTH Aachen University, Germany

A 1.4V 260pW 1mm2 65nm CMOS Temperature/pH Sensing IC Featuring Voltage-Stacking Timer and Wireless Transmitter for Stomach-Acid-Charged Tablet-Type Digital Pills with Long-Term In-Body Monitoring

You Wu¹, Kei Awano¹, Ikuro Yamane², Hiroaki Kitaike³, Masaya Kaneko³, Hisataka Maruyama⁴, Hiroshi Miyaguchi⁵, Shinya Yoshida⁵, Takumi Kobayashi⁶, Daisuke Anzai⁶, Takeshi Fujiyabu⁷, Natsuko Inagaki⁷, Kenji Takeda⁷, Toshiro Yamanaka⁷, Taichi Ito⁷, Hiroki Kawashima⁴, Mitsuhiro Fujishiro⁷, Fumihito Arai⁷, Koji Ohnishi², Kiichi Niitsu⁷

1: Kyoto University, Kyoto, Japan; 2: Otsuka Pharmaceutical Co., Ltd., Tokyo, Japan; 3: Meitec Corp., Kyoto, Japan; 4: Nagoya University, Nagoya, Japan; 5: Shibaura Institute of Technology, Tokyo, Japan; 6: Osaka Metropolitan University, Osaka, Japan; 7: The University of Tokyo, Tokyo, Japan

Implementation of Drive Signal in DC-DC Converters for Chaos Synchronization

Daniils Surmacs, Sergejs Tjukovs, Romans Kusnins, Kristaps Gailis, Dmitrijs Pikulins

Riga Technical University, Latvia

Accurate Analysis of Switching Transients in the High-Frequency, Integrated Dual-Path Step-Down DC-DC Converter

Domenico Frassetto¹, Stefano Cabizza², Asif Karim³, Giorgio Spiazzi¹, Andrea Bevilacqua¹, Andrea Neviani¹

1: University of Padova, Italy; 2: Infineon Technologies Italia S.r.l.; 3: Infineon Technologies Austria AG

A Power-Efficient Analog Integrated Neural Network for Multiple Sclerosis Disease Detection

Vassilis Alimisis¹, Konstantinos Cheliotis², Vasileios Moustakas², Anna Mylona², Andreas Papathanasiou², Paul P. Sotiriadis²

1: Archimedes, Athena Research Center, Greece; 2: National Technical University of Athens, Greece

Exploiting multi-VT FDSOI technology for improved area and energy trade-offs for ultra-low voltage Schmitt Triggers

Louisa Charlotte Nägle¹, Snorre Aunet², Ulrich Rückert¹

1: Bielefeld University, Germany; 2: Norwegian Universityof Science and Technology, Norway

Matrix-Vectorized Canonical Signed Digit Quantized Neural Networks for Efficient Forward Pass Simulation

Maria Khan, Jari Nurmi

Tampere University, Finland

Automatic Verification of Analog and Mixed-Signal Neural Network Accelerators and Matrix Multipliers

Roland Müller¹, Bijoy Kundu¹, Jan Maximilian Vieregge¹, Yogesh Patil¹, Ralf Brederlow²

1: Fraunhofer Institut for Integrated Circuits IIS, Germany; 2: Technical University of Munich, Germany

Efficient Prompt Design for Resource-Constraint Deployment of Local LLMs

Aisvarya Adeseye, Jouni Isoaho, Seppo Virtanen, Mohammad Tahir

university of Turku, Finland

Small Packets, Big Challenges: Enhancing Reliability in High-Speed, Low-Latency Inter-FPGA Communication

Vida Sobhani, Jialan Zheng, Tobias Gemmeke

RWTH Aachen, Germany

A Novel Layout–Circuit Co-Design Framework for Radiation Hardening in Nanoscale Technology

Aobo Cui, Eleonora Vacca, Luca Sterpone, Sarah Azimi

Politecnico di Torino, Italy

A (145,128) DEC-TED BCH Decoder with Composite Field and Redundant Arithmetic

Hossein Hashemi Shadmehri, Christian Lanius, Tobias Gemmeke

Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen University

Optimizing Embedded Software Platform Development: A Multi-Stage MDA-Driven Approach to Firmware Generation for Multiple Programming Languages

Raphael Kunz^1,2, Lijun Chen^1,2, Stephanie Ecker^1,3, Yash Ranjan¹, Paritosh Kumar Sinha¹, Wolfgang Ecker^1,2

1: Infineon Technologies AG; 2: Technical University of Munich, Germany; 3: ChipGlobe GmbH

Thoth: Rust-Driven Firmware and HDL Co-Design for Trusted IoT/UAV Systems

Mohamed El-Hadedy¹, Wen-Mei Hwu²

1: California Polytechnic University, United States of America; 2: UIUC, USA

All About Nothing: Towards Zero-Cost Hardware Accelerated RISC-V Interrupt Handling in Rust

Pawel Dzialo, Per Lindgren

Luleå Tekniska Universitet, Sweden

A 22nm Coarse-Grained Reconfigurable Array with Novel Features for Machine Learning and Digital Signal Processing

Waqar Hussain¹, Alexandra Geciova¹, Ralf Hekmann¹, Henry Hoffmann², Zohaib Hassan³, Jari Nurmi³

1: Nordic Semiconductor ASA, Norway; 2: Department of Computer Science, The University of Chicago, Chicago, IL, USA; 3: Wireless Research Centre, Tampere University, Tampere, Finland

A 4-W Ka-Band High Efficiency 0.15 μm GaAs Stacked Power Amplifier Design

Batuhan Dinc, Mustafa Berke Yelten

Istanbul Technical University, Turkiye