Fault-Tolerant Character Recognition in Neuromorphic Systems Using RRAM Crossbar Arrays

Fatemeh Shirinzadeh¹, Abhoy Kole¹, Kamalika Datta^1,2, Saeideh Shirinzadeh^1,3, Rolf Drechsler^1,2

1: German Research Centre for Artificial Intelligence (DFKI), Germany; 2: Institute of Computer Science, University of Bremen, Germany; 3: Fraunhofer Institute for Systems and Innovation Research (ISI), Karlsruhe, Germany

Systematic Design of a PVT-Robust CMOS Time-Based-Controlled DC-DC Converter Using Open-Source Tools

Jorge Marin^1,2, Vicente Osorio¹, Andrés Martinez¹, Daniel Arévalos³, Krzysztof Herman⁴, Juan Pablo Martínez Brito⁵, Christian A. Rojas^1,2

1: Department of Electronic Eng., Universidad Tecnica Federico Santa Maria, Valparaiso, Chile; 2: Advanced Center of Electrical and Electronics Engineering, Universidad T´ecnica Federico Santa Mar´ıa; 3: Hochschule M¨unchen University of Applied Sciences, Munich, Germany; 4: IHP – Leibniz Institute for High Performance Microelectronics, Frankfurt (Oder), Germany; 5: CEITEC Semiconductores, Porto Alegre, Brazil

Memristor Differential Pair Ternary Weight Neural (TWN) Network Architecture

Yi Zhu, Dinesh Pamunuwa, Roshan Weerasekera

University of Bristol, United Kingdom

Simopt-Power: Leveraging Simulation Metadata For Low-Power Design Synthesis

Eashan Wadhwa, Shanker Shreejith

Trinity College Dublin, Ireland

Thermal-EXAMINER: IP Extraction from MAGIC Logic-in-Memory using thermal side-channel attacks

Lorenzo Pfeifer, Antonia Weiler, Jeremy Scott Haas, Rainer Leupers, Jan Moritz Joseph

RWTH Aachen University, Germany

Evaluating Rapid Makespan Predictions for Heterogeneous Systems with Programmable Logic

Martin Wilhelm¹, Franz Freitag², Max Tzschoppe¹, Thilo Pionteck¹

1: Otto-von-Guericke University Magdeburg; 2: University of Applied Sciences Magdeburg-Stendal

KRS Unleashed: Towards a Robotics FPGA Development Environment for Rapid Prototyping

Paul Gottschaldt^1,2, Diana Goehringer^1,2

1: TU Dresden, Chair of Adaptive Dynamic Systems, Germany; 2: TU Dresden, Centre for Tactile Internet with Human-in-the-Loop (CeTI), Dresden, Germany

A Hierarchical Approach to Health Management in Heterogeneous Embedded Systems

Anton Tsertov¹, Sergei Devadze², Artur Jutman², Konstantin Shibin¹

1: Tallinn University of Technology, Estonia; 2: Testonica Lab

Towards Achieving Vertical Reuse in SoC-level Verification

Petr Bardonek¹, Alessandra Dolmeta², Marcela Zachariasova¹, Guido Masera²

1: Brno University of Technology, Czech Republic; 2: Politecnico di Torino

A Robust, Fully Integrated 30.5-33.2GHz and 34.3-36.8GHz Frequency Synthesizer in SiGe-BiCMOS for Space Applications

Frank Herzel, Seyyid Dilek, Jakub Jablonski, Falk Korndoerfer, Corrado Carta, Gunter Fischer

IHP Frankfurt (Oder)

A Foreground Calibration Scheme for Comparator Offsets in Loop-Unrolled SAR ADCs

Shaobai Xing, Pietro Andreani, Wenbo Li

lund university, Sweden

A 0.9 V StrongARM Latch Comparator with 16 ps Delay and 7.5 fJ/op in 16 nm FinFET CMOS Technology

Rafael Ferreira¹, Subrahmanyam Boyapati², Rao Bandi², Miguel Coelho³, Rafael Martins¹, Alexandra Matos¹, Pedro Toledo², Luis Oliveira^1,4,5,6, José Augusto^3,4, João Oliveira^1,4,5,6

1: NOVA School of Science and Engineering, Portugal; 2: Synopys; 3: Faculty of Sciences of the University of Lisbon, Portugal; 4: Center of Technology and Systems (CTS-UNINOVA); 5: Institute of Systems and Computer Engineering - Research and Development (INESC-ID); 6: Department of Electrical and Computer Engineering (DEEC)

Time-resolved single-photon counting IC for Raman Imaging

Leeladhar Bodu, Tuomo Talala, Jan Nissinen, Ilkka Nissinen

Circuits and Systems (CAS) research unit, University of Oulu, Finland

300mV-VDD, nW-Power, ST-DIGOTA using I/O Devices in FinFET Technology

Alexandra Matos³, Ricardo Machado^2,3, Pedro Toledo², Miguel Coelho¹, Rafael Ferreira³, Rafael Martins³, Boyapati Subrahmanyam², João Oliveira³, Luís Oliveira³, José Augusto^1,4

1: Faculty of Sciences of the University of Lisbon, Portugal; 2: Synopsys; 3: Department of Electrical and Computer Engineering (DEEC), NOVA School of Science and Technology, Center of Technology and Systems (CTS-UNINOVA), Associated Laboratory of Intelligent Systems (LASI), 2829-516 Lisbon, Portugal; 4: nstitute of Systems and Computer Engineering - Research and Development (INESC-ID)

GenIE: Reuse-Oriented Generation of Domain-Specific Instruction Extensions

Philipp van Kempen¹, Andreas Hager-Clukas², Daniel Mueller-Gritschneder³, Ulf Schlichtmann¹

1: Technical University of Munich, Germany; 2: Hochschule München, Germany; 3: TU Wien, Austria

Performance Evaluation of MAGIC-ReRAM Arithmetic Circuits for Low-Latency In-Memory Computing

Saeideh Nabipour¹, Fatemeh Shirinzadeh¹, Kamalika Datta^1,2, Abhoy Kole¹, Saeideh Shirinzadeh^1,3, Rolf Drechsler^1,2

1: Cyber-Physical Systems, DFKI GmbH, Germany; 2: University of Bremen, Germany; 3: Fraunhofer Institute for Systems and Innovation Research (ISI), Karlsruhe, Germany

Novel Verification IP (VIP) for AXI4 interconnects employing Universal Verification Methodology (UVM)

Petri Sydänmaa¹, Jaisal Ashraf¹, Mohsin Abbas²

1: Nokia Networks and Solutions, Finland; 2: Faculty of Information Technology and Communication Sciences, Tampere University

4T Bitcell for Digital Compute-in-Memory

Florian Freye, Christian Lanius, Nils Mutert, Tobias Gemmeke

Chair of Integrated Digital Systems and Circuit Design, RWTH Aachen, Germany

Rust for Safety and Security Critical Systems

Malte Munch¹, Marcus Lindner², Johan Eriksson³, Pawel Dzialo¹, Per Lindgren¹

1: Luleå University of Technology, Sweden; 2: Scania AB, Sweden; 3: Grepit AB, Sweden

Model-Driven Generation of Executable Models for Hardware Specification Validation

Robert Kunzelmann^1,2, Raymund Tonyka^1,2, Vinod Bangalore Ganesh^1,3, Raphael Kunz^1,2, Stephanie Ecker^1,4, Wolfgang Ecker^1,2

1: Infineon Technologies AG, Germany; 2: Technical University of Munich, Germany; 3: Technical University of Dresden, Germany; 4: Chipglobe GmbH, Germany

HyPPA: PPA-Aware Hierarchical RTL Generation and Evaluation of RISC-V Cores Using Hyperparameter Tuning

Mohamed Badawy^1,2, Jiulong Wang^1,2, Vijaydeep Yadav¹, Nguyen Anh Vu Doan¹, Paritosh Kumar Sinha¹, Wolfgang Ecker^1,2

1: Infineon Technologies AG; 2: Technical University of Munich

ChiselTrace: Typed Behavioral Debugging in Chisel Through Signal Dependency Tracing

Jarl Brand¹, Casper Cromjongh¹, Peter Hofstee^1,2, Zaid Al-Ars¹

1: Delft University of Technology, The Netherlands; 2: IBM Infrastructure, Austin, TX, US

A 8.9 μW 12.3-ENOB SAR ADC with <1 LSB DNL/INL for Electrochemical Impedance Spectroscopy in 12 nm CMOS

Christian Ziegler¹, Alexander Meyer¹, Fa Foster Dai², Liubov Bakhchova¹, Vadim Issakov¹

1: TU Braunschweig, Germany; 2: Guest Professor, TU Braunschweig, Germany

Design and Experimental Verification of A 0.14-0.55V 1.9-24.2pW 22nm 3-bit Binary Search Supply-to-Digital Converter Using One-Hot Hard-Wired Topology and Supply-Dependent-Activation Buffers for Supply Sensing IoT Systems

Hiroaki Kitaike¹, Hironori Tagawa¹, Kento Okamura¹, Wu You¹, Kei Awano¹, Jin Nakamura², Masaya Kaneko², Yuta Kimura³, Hiroaki Nakamura³, Shufan Xu¹, Kunyang Liu¹, Hirofumi Shinohara¹, Kiichi Niitsu¹

1: Kyoto University, Japan; 2: Meitec Corp, Japan; 3: Shuharisystem Corp, Japan

Automatic Reference Clock Duty Cycle Calibration System for Dual Edge Sampling RF Circuits

Miikka Tenhunen^1,2, Veeti Lahtinen^1,2, Marko Kosunen¹

1: Aalto University; 2: Saab Finland Oy

A 50Gbps Reference-less NRZ Full-rate Bang-Bang CDR with Automatic Frequency Acquisition in 130nm SiGe:C BiCMOS Technology

Mohammed Iftekhar^1,2, Babak Sadiye¹, Wolfgang Mueller¹, J. Christoph Scheytt¹

1: Heinz Nixdorf Institute, Paderborn University, Germany; 2: Ranovus GmbH, Nuremberg, Germany

FPGA Acceleration of Convolutional Neural Networks at the Edge: A Comparative Study on High-Level Synthesis Frameworks

João Faria^1,2, Fabio Coutinho^1,2, Arnaldo Oliveira^1,2

1: Universidade de Aveiro, Portugal; 2: Instituto de Telecomunicações, Aveiro

Improving AI Accelerator Performance Through Co-Designing Neural Networks and Systolic Hardware

Annina Gutermann, Alexey Serdyuk, Foivos Paraskevas, Hella Toto Kiesa, Fabian Lesniak, Jakob Schwarz, Michael Hartmann, Tanja Harbaum, Juergen Becker

Karlsruhe Institute of Technology, Germany

Implementation Study of a Noise Cancellation Filter for a 0–3 MASH Delta-Sigma-ADC

Jonathan Ungethüm, Nicolas Graber, Simon Wilhelmstätter, John G. Kauffman, Maurits Ortmanns

Institute of Microelectronics, University of Ulm, Germany

ATAS-HM: Adaptive Task Allocation for Real-Time Tasks on Heterogeneous Multicore Systems

Arthur Nathaniel Mwang’onda^1,2, Diana Goehringer^1,2

1: TU Dresden, Chair of Adaptive Dynamic Systems, Germany; 2: TU Dresden, Centre for Tactile Internet with Human-in-the-Loop (CeTI), Germany

An Adaptive and Secure Resource Management Architecture for Virtualized FPGAs

Zuwen Ou^1,2, Lu Jiang¹, Lester Kalms^1,2, Diana Göhringer^1,3

1: TU Dresden, Chair of Adaptive Dynamic Systems, Germany; 2: Deutsche Zentrum für Astrophysik, Postplatz 1, 02826 Görlitz, Germany; 3: TU Dresden, Centre for Tactile Internet with Human-in-the-Loop (CeTI), Germany