| Session | |
Posters Day2 and Coffee
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| Presentations | |
Design Space Exploration of Dynamically Reconfigurable Network-on-Chip Architectures with Multiobjective Evolutionary Algorithms Technische Universität Dresden, Germany RV-ProViler: Evaluating RISC-V ISA for Application-Specific Requirements Technische Universität Dresden, Germany Design of a Karatsuba Multiplier to Accelerate Digital Signature Schemes on Embedded Systems Instituto de Microelectrónica de Sevilla (IMSE-CNM), CSIC-US, Seville, Spain High linear on-chip delay generator for a depth profiling CMOS SPAD Raman sensor University of Oulu, Finland A 10 Gb/s Low-Power Single-Ended Linear Equalizer for DRAM Interfaces University of Kaiserslautern-Landau (RPTU), Germany Compact and Efficient Switching Power Amplifier for Micro-NMR Applications Linköping University, Sweden Joint CPU-FPGA Hardware-Aware Quantized Training of Graph Convolutional Networks Linköping University, Sweden FPGA-based Resource Efficient High Throughput Object Detection Using Pipelined CNN and Custom SSD Institute for Embedded Systems, University of Siegen, 57076 Siegen, Germany Radiation-Hardening-by-Design Triple Modular Redundancy Flip-Flop with Self-Correction 1IHP GmbH, Germany; 2University of Potsdam, Germany; 3Arquimea Research Center, Spain; 4IPTC, ETSI Telecomunicacion, Universidad Politecnica de Madrid, Spain Quantitative Evaluation on the Limits of SORN Arithmetic Hardware Circuits 1ITEM.me, University of Bremen, Bremen, Germany; 2Hamburg University of Applied Sciences, Hamburg, Germany | |