Conference Programme

The overview and detailed programme is posted below.

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Overview
Session
A-03: Symp A
Time:
Tuesday, 20/Jun/2017:
10:30am - 12:00pm

Session Chair: Julie Widiez, CEA, LETI, MINATEC Campus
Location: Rm 307

CMOS and III-V Integration 


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Presentations
10:30am - 11:00am
Invited

CMOS to Beyond CMOS: From Advanced Structures to Complex Material Systems

Voon Yew, Aaron THEAN

National University of Singapore, Singapore

As the semiconductor industry scales deep into the the sub-10nm technology nodes in the next decade, the need to maintain chip-level energy budget with increasing circuit density motivates the search for new materials and new transistor technologies. To increase functionality and performance, there is a trend to integrate different process technologies heterogeneously. This drives innovations from advanced structures processing to increasingly complex integration of material systems. In this paper, we will review the advanced CMOS towards Beyond-CMOS technologies that are being explored today.

The industry has started to explore beyond Silicon materials for transistors, there are enormous recent learning on how non-Si materials like III-V and Ge bring advantages over traditional silicon, as well as new challenges. Such devices typically involve the heterogeneous combination of materials. Due to the challenging material combinations, defects become the major limitations. Moreover, emerging ultra-low voltage devices like TFETs are inevitably more sensitive to defects. Therefore, defect metrology and modeling gain importance. To support high-volume manufacturing at advanced CMOS-level densities, high-throughput in-line characterization techniques will need to be developed. This remains a major challenge today.

With the mastery of heterogeneous material integration, even greater opportunities are enabled to bring in non-tranditional semiconductor material to augment or expand CMOS. There are a variety of charge-based and non-charge based Beyond-CMOS based technologies being investigated actively world-wide. New classes of ultra-thin materials from Graphene to transition Metal Dichalcogenides and their 2-D Van Der Waal Heterostructures offer a rich gamut of interesting physical properties that can be harness for new functions. There is also much interest to integrate non-charge based computational systems like spintronics with CMOS. To introduce non-volatility memory-like capabilities to logic computatons are among some of the value propositions for these new approaches.


11:00am - 11:30am
Invited

Benchmarking Source/Drain Doping and Contact Technology Options for III-V Semiconductor Devices

Rinus LEE

Globalfoundries, United States

There has been significant progress in the development of source/drain doping and contact technology options for III-V semiconductor devices. It is important that these options are benchmarked against existing data to evaluate their progress and compatibility for high volume manufacturing. The key metric for source/drain doping and contacts is to achieve low specific contact resistivity at the semiconductor-to-contact interface. In this paper, we review the basic approaches to reducing specific contact resistivity and benchmarking recent progress to established values. We believe benchmarking is critical in providing a framework to enable further development in this field.



 
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