Conference Programme

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A-02: Symp A
Monday, 19/Jun/2017:
4:00pm - 6:15pm

Session Chair: Xiao Gong, National University of Singapore
Location: Rm 307

Wafer Bonding Techniques for Heterogeneous Integration 

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4:00pm - 4:30pm

Low Power III-V MOSFETs and TFETs on Si Platform

Shinichi TAKAGI, Mitsuru TAKENAKA

Tokyo University, Japan

CMOS and tunneling-FETs (TFETs) utilizing high mobility III-V channels on Si substrates is expected to be one of the promising devices for high performance and low power integrated systems in the future technology nodes, because of the enhanced carrier transport and tunneling properties. However, the high quality III-V channel formation on Si substrates is still one of the most difficult challenges in III-V MOSFET technologies. For this purpose, we are employing direct wafer bonding of III-V channel layers to Si substrates. We have proposed and demonstrated the transfer of InGaAs grown on a Si donor wafer to Si handle wafers in order to extend this wafer bonding technology to large-size Si wafers. We demonstrated a variety of III-V devices on Si substrates, which include ultrathin body InGaAs-OI MOSFETs, Tri-gate InGaAs/InAs/InGaAs-OI QW channel MOSFETs, GaSb-OI pMOSFETs, InAs/GaSb-OI CMOS, Zn-diffused source InGaAs TFETs and InGaAs/GaAsSb-OI TFETs. Here, the formation of high mobility channels and high quality source tunnel junctions are critical issues for MOSFETs and TFETs, respectively. We address key issues to enhance the performance of III-V MOSFETs and TFETs on Si substrates.

This work was partly supported by JST-CREST. The authors would like to thank Drs. C.-Y. Chang, Dr. S.-H. Kim, D. H. Ahn, K. Nishi, M. Noguchi and T. Gotow in the University of Tokyo, Drs. O. Ichikawa, M. Yokoyama, T. Yamamoto and H. Yamada in Sumitomo Chemical Corporation and Drs. M. Mitsuhara, T. Hoshi, H. Sugiyama and H. Yokoyama in NTT, and Drs. J. Li and Y. C. Kao in IntelliEPI for their collaborations.

4:30pm - 5:00pm

Monolithic Integration of 200 mm Si-CMOS and III-V HEMT/LED through Direct Wafer Bonding

Kwang Hong LEE1, Shuyu BAO1,2, Kenneth LEE1, Eugene FITZGERALD1,3, Chuan Seng TAN1,2

1Singapore-MIT Alliance for Research & Technology, Singapore; 2Nanyang Technological University, Singapore; 3Massachusetts Institute of Technology, United States

Integration of III-V compound semiconductor and silicon CMOS on a common silicon substrate is a key enabler for opening up new circuit applications and capabilities. In the conventional hybrid approach, silicon and III–V circuits are fabricated and packaged separately, and then combined on a carrier substrate (e.g. PCB). This approach is confronted by interconnect size and losses, which affect performance, form factor, power consumption, cost, and complexity. For III/V-Si hybrid integration, direct epitaxial growth of III-V compounds on Si substrate or CMOS devices would be the most desirable approach, but the high temperature III-V materials growth would severely degrade the CMOS transistors. Wafer bonding is another promising approach to integrate III-V materials on Si substrate. In this work, wafer bonding is used to integrate III-V and silicon on a common platform to realize a novel side-by-side hybrid circuit, all within a single chip.

Integration of III-V HEMT/LED (e.g., InGaAs HEMT, InGaP LED, GaN HEMT and InGaN LED are grown directly on Si substrates) and CMOS-SOI on a common 200 mm Si substrate is demonstrated. The CMOS-SOI layer is temporarily bonded on a Si handle wafer and the Si substrate from the SOI wafer is removed. Another III-V containing Si substrate is then bonded to the CMOS-SOI layer held by the handle wafer. Finally, the handle wafer is released to realize the CMOS layer on III-V/Si hybrid structure on a common substrate. Process optimization to achieve defect-free bonding will be discussed. In addition, the wafer fragility issue of the GaN/Si substrates (both GaN HEMT and InGaN LED, in this case) will be addressed and discussed in details. Through this method, high temperature III-V materials growth can be completed without the presence of the temperature sensitive CMOS layer, hence damages to the CMOS layer is avoided.

5:00pm - 5:15pm

Growth and Wafer Bonding of GaN on 200 mm Si

Li ZHANG1, Kwang Hong LEE1, Kenneth LEE1, Soo Jin CHUA1,2, Eugene FITZGERALD1,3

1Low Energy Electronic Systems, Singapore MIT Alliance for Research and Technology, Singapore; 2Department of Electrical and Computer Engineering, National University of Singapore, Singapore; 3Department of Materials Science and Engineering, Massachusetts Institute of Technology, United States

We describe the research results produced from our focus on integrating GaN into Si CMOS integrated circuits. The 200 mm GaN on 725 um thick engineered substrates formed through a combination of MOCVD and wafer bonding processes. Our optimized 200 mm GaN-on-Si (111) epitaxial wafers have bow values < 30 um, with total III-N film thicknesses of 4.6 um including a thin (<1 um) buffer. XRD FWHM values of 290 and 280 arcsec for (002) and (102) reflections indicate TDD of less than 3×108 cm-2. High brightness InGaN/GaN MQW LEDs emitting at 450 nm with total III-N stack thickness of 4.6 um have also been demonstrated. Central emission wavelength standard deviation of < 2 nm was achieved across the entire 200 mm, wafer, and typical devices exhibited turn-on at ~2.5 V with diode ideality factor of 2.8. The integration of 200 mm GaN and CMOS wafer is initiated by a substrate replacement to address wafer fragility issues typically associated with GaN on SEMI-spec Si wafers before the double transfer process of the Si CMOS layer. This also leads new wafer/device platforms such as GaN-OI and CMOS + GaN that will open new avenues in device performance and integration of III-N with Si CMOS.

5:15pm - 5:30pm

InP Composite Substrate for Low-cost High-end RF Applications

Catherine CADIEUX1, Marc RABAROT1, Olivier LEDOUX2, Muriel MARTINEZ2, Eric GUIOT2, Gregory HOUZET3, Thierry LACREVAZ3, Bernard FLECHET3

1Laboratoire d'électronique des technologies de l'information (CEA-LETI), France; 2Soitec, France; 3Laboratoire de microelectronique electromagnetisme (IMEP-LAHC), France

InP based devices have recently attracted a great interest as an alternative to GaAs in forthcoming 5G systems[1]. More specifically, InP DHBT devices, with a high speed operating frequency and one of the highest voltage breakdown, appear as serious candidate. However, InP substrates availability, cost and fragility remain a major issue for large scale adoption. The layer transfer of InP onto GaAs via Smart CutTM technology has been previously demonstrated in photovoltaic applications to solve the cost and robustness problems[2]. We here propose a variation of this approach involving fully semi-insulating substrates adequate for RF applications. This is achieved through the integration of oxide bonding.

Even though the Smart CutTM transfer technology with oxide bonding has already matured through the development of SOI, its integration to III-V materials revealed new challenges. The bonding oxide densification, as well as the adhesive layers at III-V interfaces have been studied and will be discussed. The main difficulties do not reside in the film transfer itself, but in the thermal stabilization necessary for further RF devices epitaxies at 600ºC.

The result of these developments is a fully semi-insulating 100 mm InPOGaAs composite substrate stabilized at typical InGaAs epitaxial temperatures and exempt of interfacial voids. In order to demonstrate the device-related potential advantages of the InP composite substrate over the bulk substrate, coplanar waveguide RF characterization has also been done and will be presented.


[1] P. J. Zampardi, B. Moser, J. C. Li, D. Gamini, D. Limanto, and K. Muhonen, “Suitability of InP DHBTs in ET & APT Systems,” in 2016 IEEE Compound Semiconductor Integrated Circuit Symposium (CSICS), 2016, pp. 1–4.

[2] A. Tauzin et al., “InP-based composite substrates for four junction concentrator solar cells,” in AIP Conference Proceedings, 2016, vol. 1679, p. 40009.

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